AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC
Summary: Change-Id: I854fbf7d48e937bef9f8f3f5d0c8aeb970652630
Reviewers: rampitec, mareko
Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64807
Change-Id: I4405b3a7f84186acea5a78d291bff71056e745fc
llvm-svn: 366314
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index a23348e..885239e 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -920,7 +920,7 @@
for (const MachineOperand &Def : MI->defs()) {
MachineOperand *Op = I->findRegisterUseOperand(Def.getReg(), false, TRI);
- if (!Op || (Op->isImplicit() && Op->getReg() == AMDGPU::EXEC))
+ if (!Op)
continue;
return true;
}