commit 8b8eee5904ca677bf5336da01160ee9bd3f98444
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jul 09 14:10:43 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jul 09 14:10:43 2019 +0000
tree def85f4015eaf8464c1653ba284c31f2d4c56d77
parent e509af3cd6c92fd9607415fa40d158254fe93fec

AMDGPU/GlobalISel: Make s16 G_ICMP legal

llvm-svn: 365486

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 368cf3e..e65e56d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -337,10 +337,16 @@
 
   setAction({G_BLOCK_ADDR, CodePtr}, Legal);
 
-  getActionDefinitionsBuilder(G_ICMP)
+  auto &CmpBuilder =
+    getActionDefinitionsBuilder(G_ICMP)
     .legalForCartesianProduct(
       {S1}, {S32, S64, GlobalPtr, LocalPtr, ConstantPtr, PrivatePtr, FlatPtr})
-    .legalFor({{S1, S32}, {S1, S64}})
+    .legalFor({{S1, S32}, {S1, S64}});
+  if (ST.has16BitInsts()) {
+    CmpBuilder.legalFor({{S1, S16}});
+  }
+
+  CmpBuilder
     .widenScalarToNextPow2(1)
     .clampScalar(1, S32, S64)
     .scalarize(0)