| commit | 8bcf2f20a703c188b6dd05a8a6dba0a33a1129d8 | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Mon Jun 26 03:01:36 2017 +0000 |
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | Mon Jun 26 03:01:36 2017 +0000 |
| tree | be8d93cf0f9a28397785edf8111843ef21b1733b | |
| parent | 10fc062b2b6b52b8cf7b6da67db25792720e7384 [diff] [blame] |
AMDGPU: Whitespace fixes llvm-svn: 306265
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 81dfbe1..d0f4e00 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1234,7 +1234,7 @@ } } - if (NeedSP){ + if (NeedSP) { unsigned ReservedStackPtrOffsetReg = TRI.reservedStackPtrOffsetReg(MF); Info.setStackPtrOffsetReg(ReservedStackPtrOffsetReg);