llvm/test/CodeGen/X86/vec_set-A.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s

define <2 x i64> @test1() nounwind {
; CHECK-LABEL: test1:
; CHECK:       # BB#0:
; CHECK-NEXT:    movl $1, %eax
; CHECK-NEXT:    movd %eax, %xmm0
; CHECK-NEXT:    retl
  ret <2 x i64> < i64 1, i64 0 >
}