commit 8cd224e81ce420f4719eb4cfbcd2e77054ce25ac
author Evan Cheng <evan.cheng@apple.com> Wed Apr 25 07:12:14 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Wed Apr 25 07:12:14 2007 +0000
tree 04b5a232aa4572eb3218fa4489918d031dc29326
parent 827cb98a0a1027b69bcf288503c2577667c4eab6

Relex assertions to account for additional implicit def / use operands.

llvm-svn: 36430

llvm/lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 71bf5b0..04b08b5 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -33,7 +33,7 @@
       oc == Alpha::CPYSTs) {
     // or r1, r2, r2 
     // cpys(s|t) r1 r2 r2
-    assert(MI.getNumOperands() == 3 &&
+    assert(MI.getNumOperands() >= 3 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            MI.getOperand(2).isRegister() &&