commit 8dfcd83371503362acca50f173ee31a749f4dd72
author Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Tue Sep 25 23:33:18 2018 +0000
committer Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Tue Sep 25 23:33:18 2018 +0000
tree ce76dd4feb63b917732a39869a951f77e63f720a
parent 12c18840faa93d316a01ab3c7f778fa16403e752

[AMDGPU] Fix ds combine with subregs

Differential Revision: https://reviews.llvm.org/D52522

llvm-svn: 343047

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 3e1da95..e379e98 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -514,6 +514,7 @@
   DebugLoc DL = CI.I->getDebugLoc();
 
   unsigned BaseReg = AddrReg->getReg();
+  unsigned BaseSubReg = AddrReg->getSubReg();
   unsigned BaseRegFlags = 0;
   if (CI.BaseOff) {
     unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
@@ -525,15 +526,16 @@
 
     TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
       .addReg(ImmReg)
-      .addReg(AddrReg->getReg());
+      .addReg(AddrReg->getReg(), 0, BaseSubReg);
+    BaseSubReg = 0;
   }
 
   MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
-                                  .addReg(BaseReg, BaseRegFlags) // addr
-                                  .addImm(NewOffset0)            // offset0
-                                  .addImm(NewOffset1)            // offset1
-                                  .addImm(0)                     // gds
-                                  .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
+                        .addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
+                        .addImm(NewOffset0)                        // offset0
+                        .addImm(NewOffset1)                        // offset1
+                        .addImm(0)                                 // gds
+                        .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
 
   (void)Read2;
 
@@ -601,6 +603,7 @@
   DebugLoc DL = CI.I->getDebugLoc();
 
   unsigned BaseReg = AddrReg->getReg();
+  unsigned BaseSubReg = AddrReg->getSubReg();
   unsigned BaseRegFlags = 0;
   if (CI.BaseOff) {
     unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
@@ -612,17 +615,18 @@
 
     TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
       .addReg(ImmReg)
-      .addReg(AddrReg->getReg());
+      .addReg(AddrReg->getReg(), 0, BaseSubReg);
+    BaseSubReg = 0;
   }
 
   MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc)
-                                   .addReg(BaseReg, BaseRegFlags) // addr
-                                   .add(*Data0)                   // data0
-                                   .add(*Data1)                   // data1
-                                   .addImm(NewOffset0)            // offset0
-                                   .addImm(NewOffset1)            // offset1
-                                   .addImm(0)                     // gds
-                                   .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
+                        .addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
+                        .add(*Data0)                               // data0
+                        .add(*Data1)                               // data1
+                        .addImm(NewOffset0)                        // offset0
+                        .addImm(NewOffset1)                        // offset1
+                        .addImm(0)                                 // gds
+                        .cloneMergedMemRefs({&*CI.I, &*CI.Paired});
 
   moveInstsAfter(Write2, CI.InstsToMove);