add explicit alignment directives to assure arm code is 4-byte aligned
llvm-svn: 102030
diff --git a/compiler-rt/lib/arm/fixdfsivfp.S b/compiler-rt/lib/arm/fixdfsivfp.S
index 70d8027..30458cc 100644
--- a/compiler-rt/lib/arm/fixdfsivfp.S
+++ b/compiler-rt/lib/arm/fixdfsivfp.S
@@ -16,6 +16,7 @@
// Uses Darwin calling convention where a double precision parameter is
// passed in GPR register pair.
//
+ .align 2
DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp)
fmdrr d7, r0, r1 // load double register from R0/R1
ftosizd s15, d7 // convert double to 32-bit int into s15