commit 8e7f8df4a22b2903fd1af4a6b7da8c8d6a61ccd7
author Jim Grosbach <grosbach@apple.com> Thu Nov 18 00:46:58 2010 +0000
committer Jim Grosbach <grosbach@apple.com> Thu Nov 18 00:46:58 2010 +0000
tree 97e85e8e4bee6f26bed5ee61c2709c0b002109af
parent 28883834e18479b43cee054b46677fe0e6d654c9

Refactor a few ARM load instructions to better parameterize things and re-use
common encoding information.

llvm-svn: 119598

llvm/lib/Target/ARM/ARMInstrInfo.td

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 1121c68..a10858e 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -1134,21 +1134,21 @@
                   Pseudo, IIC_iLoad_r, "",
                   [(set GPR:$dst, (load addrmodepc:$addr))]>;
 
-def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDRH : AXI3ld<0b1011, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
+                  Pseudo, IIC_iLoad_bh_r, "",
+                  [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
+
+def PICLDRB : AXI2ldb<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
             Pseudo, IIC_iLoad_bh_r, "",
-                  [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
+                  [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
 
-def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
-            Pseudo, IIC_iLoad_bh_r, "",
-                  [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
-
-def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDRSH : AXI3ld<0b1111, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
            Pseudo, IIC_iLoad_bh_r, "",
-                  [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
+                  [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
 
-def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
+def PICLDRSB : AXI3ld<0b1101, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
            Pseudo, IIC_iLoad_bh_r, "",
-                  [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
+                  [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
 }
 let AddedComplexity = 10 in {
 def PICSTR  : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
@@ -1549,16 +1549,16 @@
 }
 
 // Loads with zero extension
-def LDRH  : AI3ldh<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
+def LDRH  : AI3ld<0b1011, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
                   IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
                   [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
 
 // Loads with sign extension
-def LDRSH : AI3ldsh<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
+def LDRSH : AI3ld<0b1111, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
                    IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
                    [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
 
-def LDRSB : AI3ldsb<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
+def LDRSB : AI3ld<0b1101, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
                    IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
                    [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;