commit 8f26840c5a63658ec3925558b18681c36a462dd8
author Bill Wendling <isanbard@gmail.com> Fri Jun 07 21:00:34 2013 +0000
committer Bill Wendling <isanbard@gmail.com> Fri Jun 07 21:00:34 2013 +0000
tree 5a124ac2e1afb76c4dc9ad58914500df3b418665
parent 52ca447fdd10d2c9411fe4bd482cc52240e35d2d

Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183571

llvm/lib/Target/X86/X86InstrInfo.cpp

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5ed8604..fca88b0 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -97,7 +97,7 @@
                     (tm.getSubtarget<X86Subtarget>().is64Bit()
                      ? X86::ADJCALLSTACKUP64
                      : X86::ADJCALLSTACKUP32)),
-    TM(tm), RI(tm, *this) {
+    TM(tm), RI(tm) {
 
   static const X86OpTblEntry OpTbl2Addr[] = {
     { X86::ADC32ri,     X86::ADC32mi,    0 },