convert bpf assembler to look like kernel verifier output
since bpf instruction set was introduced people learned to
read and understand kernel verifier output whereas llvm asm
output stayed obscure and unknown. Convert llvm to emit
assembler text similar to kernel to avoid this discrepancy
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 287300
diff --git a/llvm/test/CodeGen/BPF/alu8.ll b/llvm/test/CodeGen/BPF/alu8.ll
index c1c2bd2..73e7a8c 100644
--- a/llvm/test/CodeGen/BPF/alu8.ll
+++ b/llvm/test/CodeGen/BPF/alu8.ll
@@ -2,36 +2,36 @@
define i8 @mov(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: mov:
-; CHECK: mov r0, r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 = r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
ret i8 %b
}
define i8 @add(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: add:
-; CHECK: add r1, r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 += r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = add i8 %a, %b
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: and:
-; CHECK: and r1, r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 &= r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = and i8 %a, %b
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: bis:
-; CHECK: or r1, r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 |= r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = or i8 %a, %b
ret i8 %1
}
define i8 @xorand(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: xorand:
-; CHECK: xori r2, -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff]
+; CHECK: r2 ^= -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff]
%1 = xor i8 %b, -1
%2 = and i8 %a, %1
ret i8 %2
@@ -39,7 +39,7 @@
define i8 @xor(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: xor:
-; CHECK: xor r1, r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 ^= r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = xor i8 %a, %b
ret i8 %1
}
diff --git a/llvm/test/CodeGen/BPF/atomics.ll b/llvm/test/CodeGen/BPF/atomics.ll
index a2e17d2..c24dd65 100644
--- a/llvm/test/CodeGen/BPF/atomics.ll
+++ b/llvm/test/CodeGen/BPF/atomics.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=bpfel -verify-machineinstrs -show-mc-encoding | FileCheck %s
; CHECK-LABEL: test_load_add_32
-; CHECK: xadd32
+; CHECK: lock *(u32 *)
; CHECK: encoding: [0xc3
define void @test_load_add_32(i32* %p, i32 zeroext %v) {
entry:
@@ -10,7 +10,7 @@
}
; CHECK-LABEL: test_load_add_64
-; CHECK: xadd64
+; CHECK: lock *(u64 *)
; CHECK: encoding: [0xdb
define void @test_load_add_64(i64* %p, i64 zeroext %v) {
entry:
diff --git a/llvm/test/CodeGen/BPF/basictest.ll b/llvm/test/CodeGen/BPF/basictest.ll
index 82feb43..13a4980 100644
--- a/llvm/test/CodeGen/BPF/basictest.ll
+++ b/llvm/test/CodeGen/BPF/basictest.ll
@@ -4,12 +4,12 @@
%tmp.1 = add i32 %X, 1
ret i32 %tmp.1
; CHECK-LABEL: test0:
-; CHECK: addi r1, 1
+; CHECK: r1 += 1
}
; CHECK-LABEL: store_imm:
-; CHECK: stw 0(r1), r{{[03]}}
-; CHECK: stw 4(r2), r{{[03]}}
+; CHECK: *(u32 *)(r1 + 0) = r{{[03]}}
+; CHECK: *(u32 *)(r2 + 4) = r{{[03]}}
define i32 @store_imm(i32* %a, i32* %b) {
entry:
store i32 0, i32* %a, align 4
@@ -23,6 +23,6 @@
%tmp = load i8, i8* @G
ret i8 %tmp
; CHECK-LABEL: loadG:
-; CHECK: ld_64 r1
-; CHECK: ldb r0, 0(r1)
+; CHECK: r1 =
+; CHECK: r0 = *(u8 *)(r1 + 0)
}
diff --git a/llvm/test/CodeGen/BPF/cc_args.ll b/llvm/test/CodeGen/BPF/cc_args.ll
index 8e3f860..4ad7a22 100644
--- a/llvm/test/CodeGen/BPF/cc_args.ll
+++ b/llvm/test/CodeGen/BPF/cc_args.ll
@@ -4,32 +4,32 @@
entry:
; CHECK: test:
-; CHECK: mov r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
+; CHECK: r1 = 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00]
; CHECK: call f_i16
call void @f_i16(i16 123)
-; CHECK: mov r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
+; CHECK: r1 = 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00]
; CHECK: call f_i32
call void @f_i32(i32 12345678)
-; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
+; CHECK: r1 = 72623859790382856ll # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01]
; CHECK: call f_i64
call void @f_i64(i64 72623859790382856)
-; CHECK: mov r1, 1234
-; CHECK: mov r2, 5678
+; CHECK: r1 = 1234
+; CHECK: r2 = 5678
; CHECK: call f_i32_i32
call void @f_i32_i32(i32 1234, i32 5678)
-; CHECK: mov r1, 2
-; CHECK: mov r2, 3
-; CHECK: mov r3, 4
+; CHECK: r1 = 2
+; CHECK: r2 = 3
+; CHECK: r3 = 4
; CHECK: call f_i16_i32_i16
call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
-; CHECK: mov r1, 5
-; CHECK: ld_64 r2, 7262385979038285
-; CHECK: mov r3, 6
+; CHECK: r1 = 5
+; CHECK: r2 = 7262385979038285ll
+; CHECK: r3 = 6
; CHECK: call f_i16_i64_i16
call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
@@ -42,54 +42,54 @@
define void @f_i16(i16 %a) #0 {
; CHECK: f_i16:
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i16 %a, i16* @g_i16, align 2
ret void
}
define void @f_i32(i32 %a) #0 {
; CHECK: f_i32:
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 2) = r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00]
store volatile i32 %a, i32* @g_i32, align 2
ret void
}
define void @f_i64(i64 %a) #0 {
; CHECK: f_i64:
-; CHECK: stw 0(r2), r1
-; CHECK: stw 4(r2), r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u32 *)(r2 + 0) = r1
+; CHECK: *(u32 *)(r2 + 4) = r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00]
store volatile i64 %a, i64* @g_i64, align 2
ret void
}
define void @f_i32_i32(i32 %a, i32 %b) #0 {
; CHECK: f_i32_i32:
-; CHECK: stw 0(r3), r1
+; CHECK: *(u32 *)(r3 + 0) = r1
store volatile i32 %a, i32* @g_i32, align 4
-; CHECK: stw 0(r3), r2
+; CHECK: *(u32 *)(r3 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
ret void
}
define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
; CHECK: f_i16_i32_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: stw 0(r1), r2
+; CHECK: *(u32 *)(r1 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
; CHECK: f_i16_i64_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: std 0(r1), r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u64 *)(r1 + 0) = r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i64 %b, i64* @g_i64, align 8
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
diff --git a/llvm/test/CodeGen/BPF/cc_args_be.ll b/llvm/test/CodeGen/BPF/cc_args_be.ll
index 59a7439..4d1efcc 100644
--- a/llvm/test/CodeGen/BPF/cc_args_be.ll
+++ b/llvm/test/CodeGen/BPF/cc_args_be.ll
@@ -5,32 +5,32 @@
entry:
; CHECK: test:
-; CHECK: mov r1, 123 # encoding: [0xb7,0x10,0x00,0x00,0x00,0x00,0x00,0x7b]
+; CHECK: r1 = 123 # encoding: [0xb7,0x10,0x00,0x00,0x00,0x00,0x00,0x7b]
; CHECK: call f_i16
call void @f_i16(i16 123)
-; CHECK: mov r1, 12345678 # encoding: [0xb7,0x10,0x00,0x00,0x00,0xbc,0x61,0x4e]
+; CHECK: r1 = 12345678 # encoding: [0xb7,0x10,0x00,0x00,0x00,0xbc,0x61,0x4e]
; CHECK: call f_i32
call void @f_i32(i32 12345678)
-; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x10,0x00,0x00,0x05,0x06,0x07,0x08,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04]
+; CHECK: r1 = 72623859790382856ll # encoding: [0x18,0x10,0x00,0x00,0x05,0x06,0x07,0x08,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04]
; CHECK: call f_i64
call void @f_i64(i64 72623859790382856)
-; CHECK: mov r1, 1234
-; CHECK: mov r2, 5678
+; CHECK: r1 = 1234
+; CHECK: r2 = 5678
; CHECK: call f_i32_i32
call void @f_i32_i32(i32 1234, i32 5678)
-; CHECK: mov r1, 2
-; CHECK: mov r2, 3
-; CHECK: mov r3, 4
+; CHECK: r1 = 2
+; CHECK: r2 = 3
+; CHECK: r3 = 4
; CHECK: call f_i16_i32_i16
call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
-; CHECK: mov r1, 5
-; CHECK: ld_64 r2, 7262385979038285
-; CHECK: mov r3, 6
+; CHECK: r1 = 5
+; CHECK: r2 = 7262385979038285ll
+; CHECK: r3 = 6
; CHECK: call f_i16_i64_i16
call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
@@ -43,54 +43,54 @@
define void @f_i16(i16 %a) #0 {
; CHECK: f_i16:
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i16 %a, i16* @g_i16, align 2
ret void
}
define void @f_i32(i32 %a) #0 {
; CHECK: f_i32:
-; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]
-; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 2) = r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]
+; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i32 %a, i32* @g_i32, align 2
ret void
}
define void @f_i64(i64 %a) #0 {
; CHECK: f_i64:
-; CHECK: stw 4(r2), r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]
-; CHECK: stw 0(r2), r1
+; CHECK: *(u32 *)(r2 + 4) = r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]
+; CHECK: *(u32 *)(r2 + 0) = r1
store volatile i64 %a, i64* @g_i64, align 2
ret void
}
define void @f_i32_i32(i32 %a, i32 %b) #0 {
; CHECK: f_i32_i32:
-; CHECK: stw 0(r3), r1
+; CHECK: *(u32 *)(r3 + 0) = r1
store volatile i32 %a, i32* @g_i32, align 4
-; CHECK: stw 0(r3), r2
+; CHECK: *(u32 *)(r3 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
ret void
}
define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
; CHECK: f_i16_i32_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: stw 0(r1), r2
+; CHECK: *(u32 *)(r1 + 0) = r2
store volatile i32 %b, i32* @g_i32, align 4
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
; CHECK: f_i16_i64_i16:
-; CHECK: sth 0(r4), r1
+; CHECK: *(u16 *)(r4 + 0) = r1
store volatile i16 %a, i16* @g_i16, align 2
-; CHECK: std 0(r1), r2 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: *(u64 *)(r1 + 0) = r2 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
store volatile i64 %b, i64* @g_i64, align 8
-; CHECK: sth 0(r4), r3
+; CHECK: *(u16 *)(r4 + 0) = r3
store volatile i16 %c, i16* @g_i16, align 2
ret void
}
diff --git a/llvm/test/CodeGen/BPF/cc_ret.ll b/llvm/test/CodeGen/BPF/cc_ret.ll
index 0957492..7bd01ad 100644
--- a/llvm/test/CodeGen/BPF/cc_ret.ll
+++ b/llvm/test/CodeGen/BPF/cc_ret.ll
@@ -5,17 +5,17 @@
; CHECK: test:
; CHECK: call f_i16
-; CHECK: sth 0(r1), r0
+; CHECK: *(u16 *)(r1 + 0) = r0
%0 = call i16 @f_i16()
store volatile i16 %0, i16* @g_i16
; CHECK: call f_i32
-; CHECK: stw 0(r1), r0
+; CHECK: *(u32 *)(r1 + 0) = r0
%1 = call i32 @f_i32()
store volatile i32 %1, i32* @g_i32
; CHECK: call f_i64
-; CHECK: std 0(r1), r0
+; CHECK: *(u64 *)(r1 + 0) = r0
%2 = call i64 @f_i64()
store volatile i64 %2, i64* @g_i64
@@ -28,21 +28,21 @@
define i16 @f_i16() #0 {
; CHECK: f_i16:
-; CHECK: mov r0, 1
-; CHECK: ret
+; CHECK: r0 = 1
+; CHECK: exit
ret i16 1
}
define i32 @f_i32() #0 {
; CHECK: f_i32:
-; CHECK: mov r0, 16909060
-; CHECK: ret
+; CHECK: r0 = 16909060
+; CHECK: exit
ret i32 16909060
}
define i64 @f_i64() #0 {
; CHECK: f_i64:
-; CHECK: ld_64 r0, 72623859790382856
-; CHECK: ret
+; CHECK: r0 = 72623859790382856ll
+; CHECK: exit
ret i64 72623859790382856
}
diff --git a/llvm/test/CodeGen/BPF/cmp.ll b/llvm/test/CodeGen/BPF/cmp.ll
index b353f90..66345ab 100644
--- a/llvm/test/CodeGen/BPF/cmp.ll
+++ b/llvm/test/CodeGen/BPF/cmp.ll
@@ -17,7 +17,7 @@
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp1:
-; CHECK: jsge r2, r1
+; CHECK: if r2 s>= r1
}
; Function Attrs: nounwind readnone uwtable
@@ -37,7 +37,7 @@
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp2:
-; CHECK: jsgt r2, r1
+; CHECK: if r2 s> r1
}
; Function Attrs: nounwind readnone uwtable
@@ -57,7 +57,7 @@
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp3:
-; CHECK: jsge r1, r2
+; CHECK: if r1 s>= r2
}
; Function Attrs: nounwind readnone uwtable
@@ -77,7 +77,7 @@
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp4:
-; CHECK: jsgt r1, r2
+; CHECK: if r1 s> r2
}
; Function Attrs: nounwind readnone uwtable
@@ -86,9 +86,9 @@
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:min:
-; CHECK: jsgt r2, r1
-; CHECK: mov r1, r2
-; CHECK: mov r0, r1
+; CHECK: if r2 s> r1
+; CHECK: r1 = r2
+; CHECK: r0 = r1
}
; Function Attrs: nounwind readnone uwtable
@@ -97,7 +97,7 @@
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:minu:
-; CHECK: jgt r3, r1
+; CHECK: if r3 > r1
}
; Function Attrs: nounwind readnone uwtable
@@ -106,7 +106,7 @@
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:max:
-; CHECK: jsgt r1, r2
+; CHECK: if r1 s> r2
}
; Function Attrs: nounwind readnone uwtable
@@ -115,5 +115,5 @@
%c.a = select i1 %1, i8 %c, i8 %a
ret i8 %c.a
; CHECK-LABEL:meq:
-; CHECK: jeq r1, r2
+; CHECK: if r1 == r2
}
diff --git a/llvm/test/CodeGen/BPF/ex1.ll b/llvm/test/CodeGen/BPF/ex1.ll
index 546e5d4..2f77884 100644
--- a/llvm/test/CodeGen/BPF/ex1.ll
+++ b/llvm/test/CodeGen/BPF/ex1.ll
@@ -30,12 +30,12 @@
; CHECK-LABEL: bpf_prog1:
; CHECK: call 4
; CHECK: call 9
-; CHECK: jnei r0, 0
-; CHECK: mov r1, 622884453
-; CHECK: ld_64 r1, 7214898703899978611
+; CHECK: if r0 != 0
+; CHECK: r1 = 622884453
+; CHECK: r1 = 7214898703899978611ll
; CHECK: call 11
-; CHECK: mov r0, 0
-; CHECK: ret
+; CHECK: r0 = 0
+; CHECK: exit
br label %13
; <label>:13 ; preds = %10, %0
diff --git a/llvm/test/CodeGen/BPF/fi_ri.ll b/llvm/test/CodeGen/BPF/fi_ri.ll
index 64773b4..1245298 100644
--- a/llvm/test/CodeGen/BPF/fi_ri.ll
+++ b/llvm/test/CodeGen/BPF/fi_ri.ll
@@ -6,15 +6,15 @@
define i32 @test() #0 {
%key = alloca %struct.key_t, align 4
%1 = bitcast %struct.key_t* %key to i8*
-; CHECK: mov r1, 0
-; CHECK: stw -8(r10), r1
-; CHECK: std -16(r10), r1
-; CHECK: std -24(r10), r1
+; CHECK: r1 = 0
+; CHECK: *(u32 *)(r10 - 8) = r1
+; CHECK: *(u64 *)(r10 - 16) = r1
+; CHECK: *(u64 *)(r10 - 24) = r1
call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 20, i32 4, i1 false)
-; CHECK: mov r1, r10
-; CHECK: addi r1, -20
+; CHECK: r1 = r10
+; CHECK: r1 += -20
%2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0
-; CHECK: call test1
+; CHECK: call test1
call void @test1(i8* %2) #3
ret i32 0
}
diff --git a/llvm/test/CodeGen/BPF/intrinsics.ll b/llvm/test/CodeGen/BPF/intrinsics.ll
index 483473e..e7a9de8 100644
--- a/llvm/test/CodeGen/BPF/intrinsics.ll
+++ b/llvm/test/CodeGen/BPF/intrinsics.ll
@@ -13,8 +13,8 @@
%9 = trunc i64 %8 to i32
ret i32 %9
; CHECK-LABEL: ld_b:
-; CHECK: ldabs_b r0, r6.data + 123
-; CHECK: ldind_b r0, r6.data
+; CHECK: r0 = *(u8 *)skb[123]
+; CHECK: r0 = *(u8 *)skb[r
}
declare i64 @llvm.bpf.load.byte(i8*, i64) #1
@@ -28,8 +28,8 @@
%5 = trunc i64 %4 to i32
ret i32 %5
; CHECK-LABEL: ld_h:
-; CHECK: ldind_h r0, r6.data
-; CHECK: ldabs_h r0, r6.data + 123
+; CHECK: r0 = *(u16 *)skb[r
+; CHECK: r0 = *(u16 *)skb[123]
}
declare i64 @llvm.bpf.load.half(i8*, i64) #1
@@ -43,8 +43,8 @@
%5 = trunc i64 %4 to i32
ret i32 %5
; CHECK-LABEL: ld_w:
-; CHECK: ldind_w r0, r6.data
-; CHECK: ldabs_w r0, r6.data + 123
+; CHECK: r0 = *(u32 *)skb[r
+; CHECK: r0 = *(u32 *)skb[123]
}
declare i64 @llvm.bpf.load.word(i8*, i64) #1
@@ -78,9 +78,9 @@
; CHECK-LABEL: bswap:
; CHECK: bswap64 r1 # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
; CHECK: bswap32 r2 # encoding: [0xdc,0x02,0x00,0x00,0x20,0x00,0x00,0x00]
-; CHECK: add r2, r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r2 += r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK: bswap16 r3 # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
-; CHECK: add r2, r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r2 += r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
}
declare i64 @llvm.bswap.i64(i64) #1
diff --git a/llvm/test/CodeGen/BPF/load.ll b/llvm/test/CodeGen/BPF/load.ll
index d4ba315..881917a 100644
--- a/llvm/test/CodeGen/BPF/load.ll
+++ b/llvm/test/CodeGen/BPF/load.ll
@@ -5,7 +5,7 @@
ret i16 %1
}
; CHECK-LABEL: am1:
-; CHECK: ldh r0, 0(r1)
+; CHECK: r0 = *(u16 *)(r1 + 0)
@foo = external global i16
@@ -14,15 +14,15 @@
ret i16 %1
}
; CHECK-LABEL: am2:
-; CHECK: ldh r0, 0(r1)
+; CHECK: r0 = *(u16 *)(r1 + 0)
define i16 @am4() nounwind {
%1 = load volatile i16, i16* inttoptr(i16 32 to i16*)
ret i16 %1
}
; CHECK-LABEL: am4:
-; CHECK: mov r1, 32
-; CHECK: ldh r0, 0(r1)
+; CHECK: r1 = 32
+; CHECK: r0 = *(u16 *)(r1 + 0)
define i16 @am5(i16* %a) nounwind {
%1 = getelementptr i16, i16* %a, i16 2
@@ -30,7 +30,7 @@
ret i16 %2
}
; CHECK-LABEL: am5:
-; CHECK: ldh r0, 4(r1)
+; CHECK: r0 = *(u16 *)(r1 + 4)
%S = type { i16, i16 }
@baz = common global %S zeroinitializer, align 1
@@ -40,4 +40,4 @@
ret i16 %1
}
; CHECK-LABEL: am6:
-; CHECK: ldh r0, 2(r1)
+; CHECK: r0 = *(u16 *)(r1 + 2)
diff --git a/llvm/test/CodeGen/BPF/loops.ll b/llvm/test/CodeGen/BPF/loops.ll
index 00be54b..39278fe 100644
--- a/llvm/test/CodeGen/BPF/loops.ll
+++ b/llvm/test/CodeGen/BPF/loops.ll
@@ -10,7 +10,7 @@
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: add:
-; CHECK: add r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} += r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -32,7 +32,7 @@
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: sub:
-; CHECK: sub r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} -= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = sub i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -54,7 +54,7 @@
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: or:
-; CHECK: or r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} |= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = or i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -76,7 +76,7 @@
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: xor:
-; CHECK: xor r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} ^= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = xor i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
@@ -98,7 +98,7 @@
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1]
; CHECK-LABEL: and:
-; CHECK: and r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: r{{[0-9]+}} &= r{{[0-9]+}}
%tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1]
%add = and i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%inc = add i16 %i.010, 1 ; <i16> [#uses=2]
diff --git a/llvm/test/CodeGen/BPF/sanity.ll b/llvm/test/CodeGen/BPF/sanity.ll
index 7f0ef88..f318c3a9 100644
--- a/llvm/test/CodeGen/BPF/sanity.ll
+++ b/llvm/test/CodeGen/BPF/sanity.ll
@@ -7,7 +7,7 @@
%1 = add nsw i32 %b, %a
ret i32 %1
; CHECK-LABEL: foo_int:
-; CHECK: add r2, r1
+; CHECK: r2 += r1
}
; Function Attrs: nounwind readnone uwtable
@@ -15,9 +15,9 @@
%1 = add i8 %b, %a
ret i8 %1
; CHECK-LABEL: foo_char:
-; CHECK: add r2, r1
-; CHECK: slli r2, 56
-; CHECK: srai r2, 56
+; CHECK: r2 += r1
+; CHECK: r2 <<= 56
+; CHECK: r2 s>>= 56
}
; Function Attrs: nounwind readnone uwtable
@@ -26,9 +26,9 @@
%2 = sub i64 %1, %c
ret i64 %2
; CHECK-LABEL: foo_ll:
-; CHECK: add r2, r1
-; CHECK: sub r2, r3
-; CHECK: mov r0, r2
+; CHECK: r2 += r1
+; CHECK: r2 -= r3
+; CHECK: r0 = r2
}
; Function Attrs: nounwind uwtable
@@ -37,9 +37,9 @@
tail call void @foo_2arg(i8 signext %1, i32 %a) #3
ret void
; CHECK-LABEL: foo_call2:
-; CHECK: slli r2, 56
-; CHECK: srai r2, 56
-; CHECK: mov r1, r2
+; CHECK: r2 <<= 56
+; CHECK: r2 s>>= 56
+; CHECK: r1 = r2
}
declare void @foo_2arg(i8 signext, i32) #2
@@ -60,7 +60,7 @@
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL: foo_cmp:
-; CHECK: jsgt r2, r1
+; CHECK: if r2 s> r1
}
; Function Attrs: nounwind readnone uwtable
@@ -82,7 +82,7 @@
%.0 = phi i32 [ %4, %2 ], [ %7, %5 ]
ret i32 %.0
; CHECK-LABEL: foo_muldiv:
-; CHECK: mul r2, r3
+; CHECK: r2 *= r3
}
; Function Attrs: nounwind uwtable
@@ -90,11 +90,11 @@
%1 = tail call i32 @manyarg(i32 1, i32 2, i32 3, i32 4, i32 5) #3
ret i32 %1
; CHECK-LABEL: foo_optimized:
-; CHECK: mov r1, 1
-; CHECK: mov r2, 2
-; CHECK: mov r3, 3
-; CHECK: mov r4, 4
-; CHECK: mov r5, 5
+; CHECK: r1 = 1
+; CHECK: r2 = 2
+; CHECK: r3 = 3
+; CHECK: r4 = 4
+; CHECK: r5 = 5
}
declare i32 @manyarg(i32, i32, i32, i32, i32) #2
@@ -105,7 +105,7 @@
%1 = getelementptr inbounds [9 x i8], [9 x i8]* %fmt, i64 0, i64 0
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @foo_printf.fmt, i64 0, i64 0), i64 9, i32 1, i1 false)
; CHECK-LABEL: foo_printf:
-; CHECK: ld_64 r1, 729618802566522216
+; CHECK: r1 = 729618802566522216ll
%2 = call i32 (i8*, ...) @printf(i8* %1) #3
ret void
}
diff --git a/llvm/test/CodeGen/BPF/setcc.ll b/llvm/test/CodeGen/BPF/setcc.ll
index f6c6db6..294c493 100644
--- a/llvm/test/CodeGen/BPF/setcc.ll
+++ b/llvm/test/CodeGen/BPF/setcc.ll
@@ -7,7 +7,7 @@
ret i16 %t3
}
; CHECK-LABEL: sccweqand:
-; CHECK: jeq r1, r2
+; CHECK: if r1 == r2
define i16 @sccwneand(i16 %a, i16 %b) nounwind {
%t1 = and i16 %a, %b
@@ -16,7 +16,7 @@
ret i16 %t3
}
; CHECK-LABEL: sccwneand:
-; CHECK: jne r1, r2
+; CHECK: if r1 != r2
define i16 @sccwne(i16 %a, i16 %b) nounwind {
%t1 = icmp ne i16 %a, %b
@@ -24,7 +24,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwne:
-; CHECK: jne r1, r2
+; CHECK: if r1 != r2
define i16 @sccweq(i16 %a, i16 %b) nounwind {
%t1 = icmp eq i16 %a, %b
@@ -32,7 +32,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccweq:
-; CHECK: jeq r1, r2
+; CHECK: if r1 == r2
define i16 @sccwugt(i16 %a, i16 %b) nounwind {
%t1 = icmp ugt i16 %a, %b
@@ -40,7 +40,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwugt:
-; CHECK: jgt r1, r2
+; CHECK: if r1 > r2
define i16 @sccwuge(i16 %a, i16 %b) nounwind {
%t1 = icmp uge i16 %a, %b
@@ -48,7 +48,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwuge:
-; CHECK: jge r1, r2
+; CHECK: if r1 >= r2
define i16 @sccwult(i16 %a, i16 %b) nounwind {
%t1 = icmp ult i16 %a, %b
@@ -56,7 +56,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwult:
-; CHECK: jgt r2, r1
+; CHECK: if r2 > r1
define i16 @sccwule(i16 %a, i16 %b) nounwind {
%t1 = icmp ule i16 %a, %b
@@ -64,7 +64,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwule:
-; CHECK: jge r2, r1
+; CHECK: if r2 >= r1
define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
%t1 = icmp sgt i16 %a, %b
@@ -72,7 +72,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwsgt:
-; CHECK: jsgt r1, r2
+; CHECK: if r1 s> r2
define i16 @sccwsge(i16 %a, i16 %b) nounwind {
%t1 = icmp sge i16 %a, %b
@@ -80,7 +80,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwsge:
-; CHECK: jsge r1, r2
+; CHECK: if r1 s>= r2
define i16 @sccwslt(i16 %a, i16 %b) nounwind {
%t1 = icmp slt i16 %a, %b
@@ -88,7 +88,7 @@
ret i16 %t2
}
; CHECK-LABEL:sccwslt:
-; CHECK: jsgt r2, r1
+; CHECK: if r2 s> r1
define i16 @sccwsle(i16 %a, i16 %b) nounwind {
%t1 = icmp sle i16 %a, %b
@@ -96,4 +96,4 @@
ret i16 %t2
}
; CHECK-LABEL:sccwsle:
-; CHECK: jsge r2, r1
+; CHECK: if r2 s>= r1
diff --git a/llvm/test/CodeGen/BPF/shifts.ll b/llvm/test/CodeGen/BPF/shifts.ll
index cb000b9..15e228c 100644
--- a/llvm/test/CodeGen/BPF/shifts.ll
+++ b/llvm/test/CodeGen/BPF/shifts.ll
@@ -3,7 +3,7 @@
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr8:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i8 %a, %cnt
ret i8 %shr
}
@@ -11,7 +11,7 @@
define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr8:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i8 %a, %cnt
ret i8 %shr
}
@@ -19,7 +19,7 @@
define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK: shl8
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i8 %a, %cnt
ret i8 %shl
}
@@ -27,7 +27,7 @@
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr16:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i16 %a, %cnt
ret i16 %shr
}
@@ -35,7 +35,7 @@
define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr16:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i16 %a, %cnt
ret i16 %shr
}
@@ -43,7 +43,7 @@
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl16:
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i16 %a, %cnt
ret i16 %shl
}
@@ -51,8 +51,8 @@
define zeroext i32 @lshr32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr32:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: slli r1, 32 # encoding: [0x67,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= 32 # encoding: [0x67,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
%shr = lshr i32 %a, %cnt
ret i32 %shr
}
@@ -60,7 +60,7 @@
define signext i32 @ashr32(i32 signext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr32:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i32 %a, %cnt
ret i32 %shr
}
@@ -68,7 +68,7 @@
define zeroext i32 @shl32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl32:
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i32 %a, %cnt
ret i32 %shl
}
@@ -76,7 +76,7 @@
define zeroext i64 @lshr64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr64:
-; CHECK: srl r1, r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i64 %a, %cnt
ret i64 %shr
}
@@ -84,7 +84,7 @@
define signext i64 @ashr64(i64 signext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr64:
-; CHECK: sra r1, r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i64 %a, %cnt
ret i64 %shr
}
@@ -92,9 +92,9 @@
define zeroext i64 @shl64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl64:
-; CHECK: sll r1, r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i64 %a, %cnt
ret i64 %shl
}
diff --git a/llvm/test/CodeGen/BPF/sockex2.ll b/llvm/test/CodeGen/BPF/sockex2.ll
index b3e83ea..d5f070e 100644
--- a/llvm/test/CodeGen/BPF/sockex2.ll
+++ b/llvm/test/CodeGen/BPF/sockex2.ll
@@ -309,11 +309,10 @@
flow_dissector.exit.thread: ; preds = %86, %12, %196, %199
ret i32 0
; CHECK-LABEL: bpf_prog2:
-; CHECK: ldabs_h r0, r6.data + 12 # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
-; CHECK: ldabs_h r0, r6.data + 16 # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
+; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
+; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
; CHECK: implicit-def: %R1
-; CHECK: ld_64 r1
-; CHECK-NOT: ori
+; CHECK: r1 =
; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
}
diff --git a/llvm/test/CodeGen/BPF/undef.ll b/llvm/test/CodeGen/BPF/undef.ll
index ef712c4..1a925cc 100644
--- a/llvm/test/CodeGen/BPF/undef.ll
+++ b/llvm/test/CodeGen/BPF/undef.ll
@@ -15,48 +15,48 @@
define i32 @ebpf_filter(%struct.__sk_buff* nocapture readnone %ebpf_packet) #0 section "socket1" {
%key = alloca %struct.routing_key_2, align 1
%1 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 0
-; CHECK: mov r1, 5
-; CHECK: stb -8(r10), r1
+; CHECK: r1 = 5
+; CHECK: *(u8 *)(r10 - 8) = r1
store i8 5, i8* %1, align 1
%2 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 1
-; CHECK: mov r1, 6
-; CHECK: stb -7(r10), r1
+; CHECK: r1 = 6
+; CHECK: *(u8 *)(r10 - 7) = r1
store i8 6, i8* %2, align 1
%3 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 2
-; CHECK: mov r1, 7
-; CHECK: stb -6(r10), r1
+; CHECK: r1 = 7
+; CHECK: *(u8 *)(r10 - 6) = r1
store i8 7, i8* %3, align 1
%4 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 3
-; CHECK: mov r1, 8
-; CHECK: stb -5(r10), r1
+; CHECK: r1 = 8
+; CHECK: *(u8 *)(r10 - 5) = r1
store i8 8, i8* %4, align 1
%5 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 4
-; CHECK: mov r1, 9
-; CHECK: stb -4(r10), r1
+; CHECK: r1 = 9
+; CHECK: *(u8 *)(r10 - 4) = r1
store i8 9, i8* %5, align 1
%6 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 5
-; CHECK: mov r1, 10
-; CHECK: stb -3(r10), r1
+; CHECK: r1 = 10
+; CHECK: *(u8 *)(r10 - 3) = r1
store i8 10, i8* %6, align 1
%7 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 1, i32 0, i64 0
-; CHECK: mov r1, r10
-; CHECK: addi r1, -2
-; CHECK: mov r2, 0
-; CHECK: sth 6(r1), r2
-; CHECK: sth 4(r1), r2
-; CHECK: sth 2(r1), r2
-; CHECK: sth 24(r10), r2
-; CHECK: sth 22(r10), r2
-; CHECK: sth 20(r10), r2
-; CHECK: sth 18(r10), r2
-; CHECK: sth 16(r10), r2
-; CHECK: sth 14(r10), r2
-; CHECK: sth 12(r10), r2
-; CHECK: sth 10(r10), r2
-; CHECK: sth 8(r10), r2
-; CHECK: sth 6(r10), r2
-; CHECK: sth -2(r10), r2
-; CHECK: sth 26(r10), r2
+; CHECK: r1 = r10
+; CHECK: r1 += -2
+; CHECK: r2 = 0
+; CHECK: *(u16 *)(r1 + 6) = r2
+; CHECK: *(u16 *)(r1 + 4) = r2
+; CHECK: *(u16 *)(r1 + 2) = r2
+; CHECK: *(u16 *)(r10 + 24) = r2
+; CHECK: *(u16 *)(r10 + 22) = r2
+; CHECK: *(u16 *)(r10 + 20) = r2
+; CHECK: *(u16 *)(r10 + 18) = r2
+; CHECK: *(u16 *)(r10 + 16) = r2
+; CHECK: *(u16 *)(r10 + 14) = r2
+; CHECK: *(u16 *)(r10 + 12) = r2
+; CHECK: *(u16 *)(r10 + 10) = r2
+; CHECK: *(u16 *)(r10 + 8) = r2
+; CHECK: *(u16 *)(r10 + 6) = r2
+; CHECK: *(u16 *)(r10 - 2) = r2
+; CHECK: *(u16 *)(r10 + 26) = r2
call void @llvm.memset.p0i8.i64(i8* %7, i8 0, i64 30, i32 1, i1 false)
%8 = call i32 (%struct.bpf_map_def*, %struct.routing_key_2*, ...) bitcast (i32 (...)* @bpf_map_lookup_elem to i32 (%struct.bpf_map_def*, %struct.routing_key_2*, ...)*)(%struct.bpf_map_def* nonnull @routing, %struct.routing_key_2* nonnull %key) #3
ret i32 undef