commit 90bdfb3daf7871ab324ff151b36cb0e783034706
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jul 15 18:31:10 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jul 15 18:31:10 2019 +0000
tree 9dd1f2175a68a79f620515556c61383606fa5316
parent 53fa759ff5a2ccc742c2d5138c4b1c04ead201ae

AMDGPU/GlobalISel: Widen vector extracts

llvm-svn: 366103

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index df58e7d..090208e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -634,11 +634,14 @@
 
     getActionDefinitionsBuilder(Op)
       .legalIf([=](const LegalityQuery &Query) {
-          const LLT &VecTy = Query.Types[VecTypeIdx];
-          const LLT &IdxTy = Query.Types[IdxTypeIdx];
-          return VecTy.getSizeInBits() % 32 == 0 &&
-            VecTy.getSizeInBits() <= 512 &&
-            IdxTy.getSizeInBits() == 32;
+          const LLT EltTy = Query.Types[EltTypeIdx];
+          const LLT VecTy = Query.Types[VecTypeIdx];
+          const LLT IdxTy = Query.Types[IdxTypeIdx];
+          return (EltTy.getSizeInBits() == 16 ||
+                  EltTy.getSizeInBits() % 32 == 0) &&
+                 VecTy.getSizeInBits() % 32 == 0 &&
+                 VecTy.getSizeInBits() <= 512 &&
+                 IdxTy.getSizeInBits() == 32;
         })
       .clampScalar(EltTypeIdx, S32, S64)
       .clampScalar(VecTypeIdx, S32, S64)