AMDGPU: Remove global isGCN predicates
These are problematic because they apply to everything,
and can easily clobber whatever more specific predicate
you are trying to add to a function.
Currently instructions use SubtargetPredicate/PredicateControl
to apply this to patterns applied to an instruction definition,
but not to free standing Pats. Add a wrapper around Pat
so the special PredicateControls requirements can be appended
to the final predicate list like how Mips does it.
llvm-svn: 314742
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index e66bf40..4fbef5c 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -537,25 +537,23 @@
// DS Patterns
//===----------------------------------------------------------------------===//
-let Predicates = [isGCN] in {
-
-def : Pat <
+def : GCNPat <
(int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
(DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
>;
-class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
+class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
(inst $ptr, (as_i16imm $offset), (i1 0))
>;
multiclass DSReadPat_Hi16 <DS_Pseudo inst, PatFrag frag, ValueType vt = i16> {
- def : Pat <
+ def : GCNPat <
(build_vector vt:$lo, (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))),
(v2i16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo))
>;
- def : Pat <
+ def : GCNPat <
(build_vector f16:$lo, (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))))),
(v2f16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo))
>;
@@ -577,14 +575,14 @@
} // End AddedComplexity = 100
-def : Pat <
+def : GCNPat <
(v2i32 (load_local_m0 (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
i8:$offset1))),
(DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
>;
-let Predicates = [HasD16LoadStore] in {
+let OtherPredicates = [HasD16LoadStore] in {
let AddedComplexity = 100 in {
defm : DSReadPat_Hi16<DS_READ_U16_D16_HI, load_local>;
defm : DSReadPat_Hi16<DS_READ_U8_D16_HI, az_extloadi8_local>;
@@ -592,7 +590,7 @@
}
}
-class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
+class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
(frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
(inst $ptr, $value, (as_i16imm $offset), (i1 0))
>;
@@ -603,7 +601,7 @@
def : DSWritePat <DS_WRITE_B16, i16, store_local_m0>;
def : DSWritePat <DS_WRITE_B32, i32, store_local_m0>;
-let Predicates = [HasD16LoadStore] in {
+let OtherPredicates = [HasD16LoadStore] in {
def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_local_hi16>;
def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_local_hi16>;
}
@@ -613,7 +611,7 @@
def : DSWritePat <DS_WRITE_B64, v2i32, store_align8_local_m0>;
} // End AddedComplexity = 100
-def : Pat <
+def : GCNPat <
(store_local_m0 v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
i8:$offset1)),
(DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
@@ -621,12 +619,12 @@
(i1 0))
>;
-class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
+class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
(inst $ptr, $value, (as_i16imm $offset), (i1 0))
>;
-class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
+class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
(inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
>;
@@ -663,8 +661,6 @@
def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
-} // let Predicates = [isGCN]
-
//===----------------------------------------------------------------------===//
// Real instructions
//===----------------------------------------------------------------------===//