[AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operands
See bug 39292: https://bugs.llvm.org/show_bug.cgi?id=39292
Reviewers: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D62660
llvm-svn: 362400
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index b77deea..307f0cb 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -916,11 +916,9 @@
case 237: return createRegOperand(SRC_PRIVATE_BASE);
case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
- // ToDo: no support for vccz register
- case 251: break;
- // ToDo: no support for execz register
- case 252: break;
- case 253: return createRegOperand(SCC);
+ case 251: return createRegOperand(SRC_VCCZ);
+ case 252: return createRegOperand(SRC_EXECZ);
+ case 253: return createRegOperand(SRC_SCC);
case 254: return createRegOperand(LDS_DIRECT);
default: break;
}
@@ -942,6 +940,9 @@
case 237: return createRegOperand(SRC_PRIVATE_BASE);
case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
+ case 251: return createRegOperand(SRC_VCCZ);
+ case 252: return createRegOperand(SRC_EXECZ);
+ case 253: return createRegOperand(SRC_SCC);
default: break;
}
return errOperand(Val, "unknown operand encoding " + Twine(Val));