[RISCV] Add support for the various RISC-V FMA instruction variants
Adds support for the various RISC-V FMA instructions (fmadd, fmsub, fnmsub, fnmadd).
The criteria for choosing whether a fused add or subtract is used, as well as
whether the product is negated or not, is whether some of the arguments to the
llvm.fma.* intrinsic are negated or not. In the tests, extraneous fadd
instructions were added to avoid the negation being performed using a xor
trick, which prevented the proper FMA forms from being selected and thus
tested.
The FMA instruction patterns might seem incorrect (e.g., fnmadd: -rs1 * rs2 -
rs3), but they should be correct. The misleading names were inherited from
MIPS, where the negation happens after computing the sum.
The llvm.fmuladd.* intrinsics still do not generate RISC-V FMA instructions,
as that depends on TargetLowering::isFMAFasterthanFMulAndFAdd.
Some comments in the test files about what type of instructions are there
tested were updated, to better reflect the current content of those test
files.
Differential Revision: https://reviews.llvm.org/D54205
Patch by Luís Marques.
llvm-svn: 349023
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
index a9bdf68..cd3a1d9 100644
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -2,6 +2,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
+; These tests are each targeted at a particular RISC-V FPU instruction. Most
+; other files in this folder exercise LLVM IR instructions that don't directly
+; match a RISC-V instruction.
+
define double @fadd_d(double %a, double %b) nounwind {
; RV32IFD-LABEL: fadd_d:
; RV32IFD: # %bb.0:
@@ -277,3 +281,118 @@
%2 = zext i1 %1 to i32
ret i32 %2
}
+
+declare double @llvm.fma.f64(double, double, double)
+
+define double @fmadd_d(double %a, double %b, double %c) nounwind {
+; RV32IFD-LABEL: fmadd_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a4, 8(sp)
+; RV32IFD-NEXT: sw a5, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft2, 8(sp)
+; RV32IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
+ ret double %1
+}
+
+define double @fmsub_d(double %a, double %b, double %c) nounwind {
+; RV32IFD-LABEL: fmsub_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: sw a4, 8(sp)
+; RV32IFD-NEXT: sw a5, 12(sp)
+; RV32IFD-NEXT: fld ft2, 8(sp)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI15_0)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI15_0)
+; RV32IFD-NEXT: fld ft3, 0(a0)
+; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %c_ = fadd double 0.0, %c ; avoid negation using xor
+ %negc = fsub double -0.0, %c_
+ %1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
+ ret double %1
+}
+
+define double @fnmadd_d(double %a, double %b, double %c) nounwind {
+; RV32IFD-LABEL: fnmadd_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: sw a4, 8(sp)
+; RV32IFD-NEXT: sw a5, 12(sp)
+; RV32IFD-NEXT: fld ft2, 8(sp)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI16_0)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI16_0)
+; RV32IFD-NEXT: fld ft3, 0(a0)
+; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT: fnmadd.d ft0, ft1, ft0, ft2
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %a_ = fadd double 0.0, %a
+ %c_ = fadd double 0.0, %c
+ %nega = fsub double -0.0, %a_
+ %negc = fsub double -0.0, %c_
+ %1 = call double @llvm.fma.f64(double %nega, double %b, double %negc)
+ ret double %1
+}
+
+define double @fnmsub_d(double %a, double %b, double %c) nounwind {
+; RV32IFD-LABEL: fnmsub_d:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: addi sp, sp, -16
+; RV32IFD-NEXT: sw a4, 8(sp)
+; RV32IFD-NEXT: sw a5, 12(sp)
+; RV32IFD-NEXT: fld ft0, 8(sp)
+; RV32IFD-NEXT: sw a2, 8(sp)
+; RV32IFD-NEXT: sw a3, 12(sp)
+; RV32IFD-NEXT: fld ft1, 8(sp)
+; RV32IFD-NEXT: sw a0, 8(sp)
+; RV32IFD-NEXT: sw a1, 12(sp)
+; RV32IFD-NEXT: fld ft2, 8(sp)
+; RV32IFD-NEXT: lui a0, %hi(.LCPI17_0)
+; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI17_0)
+; RV32IFD-NEXT: fld ft3, 0(a0)
+; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
+; RV32IFD-NEXT: fsd ft0, 8(sp)
+; RV32IFD-NEXT: lw a0, 8(sp)
+; RV32IFD-NEXT: lw a1, 12(sp)
+; RV32IFD-NEXT: addi sp, sp, 16
+; RV32IFD-NEXT: ret
+ %a_ = fadd double 0.0, %a
+ %nega = fsub double -0.0, %a_
+ %1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
+ ret double %1
+}