Extract LaneBitmask into a separate type
Specifically avoid implicit conversions from/to integral types to
avoid potential errors when changing the underlying type. For example,
a typical initialization of a "full" mask was "LaneMask = ~0u", which
would result in a value of 0x00000000FFFFFFFF if the type was extended
to uint64_t.
Differential Revision: https://reviews.llvm.org/D27454
llvm-svn: 289820
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index bda0a44..8c4b24a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1027,7 +1027,8 @@
return RC;
// We can assume that each lane corresponds to one 32-bit register.
- unsigned Count = countPopulation(getSubRegIndexLaneMask(SubIdx));
+ LaneBitmask::Type Mask = getSubRegIndexLaneMask(SubIdx).getAsInteger();
+ unsigned Count = countPopulation(Mask);
if (isSGPRClass(RC)) {
switch (Count) {
case 1:
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index 938bdca..4463761 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -234,13 +234,13 @@
RegisterSet LiveIns;
RegisterSet Tmp;
for (auto I : B.liveins()) {
- if (I.LaneMask == ~LaneBitmask(0)) {
+ if (I.LaneMask.all()) {
Tmp.insert({I.PhysReg,0});
continue;
}
for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) {
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if (M & I.LaneMask)
+ if (!(M & I.LaneMask).none())
Tmp.insert({S.getSubReg(), 0});
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index f0e9c59..55978a63 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -369,7 +369,7 @@
if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
return false;
LaneBitmask SLM = getLaneMask(DR, DSR);
- return (SLM & LM) != 0;
+ return !(SLM & LM).none();
};
// The splitting step will create pairs of predicated definitions without
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp
index 963b04b..04052b7 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp
@@ -30,7 +30,7 @@
namespace rdf {
raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P) {
- if (P.Mask != ~LaneBitmask(0))
+ if (!P.Mask.all())
OS << ':' << PrintLaneMask(P.Mask);
return OS;
}
@@ -662,7 +662,7 @@
RegisterRef NR = normalize(RR);
auto F = Masks.find(NR.Reg);
if (F != Masks.end()) {
- if (F->second & NR.Mask)
+ if (!(F->second & NR.Mask).none())
return true;
}
if (CheckUnits) {
@@ -676,7 +676,7 @@
bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
// Always have a cover for empty lane mask.
RegisterRef NR = normalize(RR);
- if (!NR.Mask)
+ if (NR.Mask.none())
return true;
auto F = Masks.find(NR.Reg);
if (F == Masks.end())
@@ -717,7 +717,7 @@
if (F == Masks.end())
return *this;
LaneBitmask NewM = F->second & ~NR.Mask;
- if (NewM == LaneBitmask(0))
+ if (NewM.none())
Masks.erase(F);
else
F->second = NewM;
@@ -1089,7 +1089,7 @@
RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
if (AR.Reg == BR.Reg) {
LaneBitmask M = AR.Mask & BR.Mask;
- return M ? RegisterRef(AR.Reg, M) : RegisterRef();
+ return !M.none() ? RegisterRef(AR.Reg, M) : RegisterRef();
}
#ifndef NDEBUG
RegisterRef NAR = normalizeRef(AR);
@@ -1211,7 +1211,7 @@
// This can happen when the register has only one unit, or when the
// unit corresponds to explicit aliasing. In such cases, the lane mask
// from RegisterRef should be ignored.
- if (!PA.second || !PB.second)
+ if (PA.second.none() || PB.second.none())
return true;
// At this point the common unit corresponds to a subregister. The lane
@@ -1221,7 +1221,7 @@
// while the lane mask of r2 in d1 may be 0b0001.
LaneBitmask LA = PA.second & RA.Mask;
LaneBitmask LB = PB.second & RB.Mask;
- if (LA != 0 && LB != 0) {
+ if (!LA.none() && !LB.none()) {
unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI);
// If register units were guaranteed to only have 1 bit in any lane
// mask, the code below would not be necessary. This is because LA
@@ -1232,7 +1232,7 @@
const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root);
LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA);
LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB);
- if (MaskA & MaskB & RC.LaneMask)
+ if (!(MaskA & MaskB & RC.LaneMask).none())
return true;
}
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.h b/llvm/lib/Target/Hexagon/RDFGraph.h
index 2e9a6cc..b279752 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.h
+++ b/llvm/lib/Target/Hexagon/RDFGraph.h
@@ -403,9 +403,9 @@
LaneBitmask Mask;
RegisterRef() : RegisterRef(0) {}
- explicit RegisterRef(RegisterId R, LaneBitmask M = ~LaneBitmask(0))
- : Reg(R), Mask(R != 0 ? M : 0) {}
- operator bool() const { return Reg != 0 && Mask != LaneBitmask(0); }
+ explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
+ : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
+ operator bool() const { return Reg != 0 && !Mask.none(); }
bool operator== (const RegisterRef &RR) const {
return Reg == RR.Reg && Mask == RR.Mask;
}
@@ -458,7 +458,7 @@
uint32_t find(T Val) const {
auto F = llvm::find(Map, Val);
assert(F != Map.end());
- return *F;
+ return F - Map.begin();
}
private:
std::vector<T> Map;
@@ -468,15 +468,15 @@
LaneMaskIndex() = default;
LaneBitmask getLaneMaskForIndex(uint32_t K) const {
- return K == 0 ? ~LaneBitmask(0) : get(K);
+ return K == 0 ? LaneBitmask::getAll() : get(K);
}
uint32_t getIndexForLaneMask(LaneBitmask LM) {
- assert(LM != LaneBitmask(0));
- return LM == ~LaneBitmask(0) ? 0 : insert(LM);
+ assert(!LM.none());
+ return LM.all() ? 0 : insert(LM);
}
uint32_t getIndexForLaneMask(LaneBitmask LM) const {
- assert(LM != LaneBitmask(0));
- return LM == ~LaneBitmask(0) ? 0 : find(LM);
+ assert(!LM.none());
+ return LM.all() ? 0 : find(LM);
}
PackedRegisterRef pack(RegisterRef RR) {
return { RR.Reg, getIndexForLaneMask(RR.Mask) };
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
index 55b1de0..3563d05 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
@@ -659,7 +659,7 @@
RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(PUA));
for (const std::pair<RegisterId,NodeRefSet> &T : RUs) {
// Check if T.first aliases UR?
- LaneBitmask M = 0;
+ LaneBitmask M;
for (std::pair<NodeId,LaneBitmask> P : T.second)
M |= P.second;
@@ -710,7 +710,7 @@
}
do {
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if (M & P.second)
+ if (!(M & P.second).none())
LV.push_back(RegisterRef(S.getSubReg()));
++S;
} while (S.isValid());
@@ -759,7 +759,7 @@
}
do {
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
- if (M & I.LaneMask)
+ if (!(M & I.LaneMask).none())
LV.set(S.getSubReg());
++S;
} while (S.isValid());
@@ -1001,7 +1001,7 @@
RegisterAggr &Local = LiveMap[B];
RefMap &LON = PhiLON[B];
for (auto &R : LON) {
- LaneBitmask M = 0;
+ LaneBitmask M;
for (auto P : R.second)
M |= P.second;
Local.insert(RegisterRef(R.first,M));