commit 92ec3bd50b3c58e6b8fea84126f1ac869ede2548
author Akira Hatanaka <ahatanaka@mips.com> Sat Sep 07 00:26:26 2013 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Sat Sep 07 00:26:26 2013 +0000
tree c9e535cb182d410637d43ca571b43778265057cc
parent d9e5ff24e6e209d614d77e611917fed9e80bd711

[mips] Place parentheses around && to silence warning.

llvm-svn: 190234

llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp

diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
index 231d485..26321c9 100644
--- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
+++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
@@ -232,9 +232,9 @@
   case Mips::BEQ:
     // beq $zero, $zero, $L2 => b $L2
     // beq $r0, $zero, $L2 => beqz $r0, $L2
-    return isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
-           printAlias("b", MI, 2, OS) ||
-           isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
+    return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
+            printAlias("b", MI, 2, OS)) ||
+           (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
   case Mips::BEQ64:
     // beq $r0, $zero, $L2 => beqz $r0, $L2
     return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);