commit 92fd05ecdcd8d5110c467645f67e1d2dd06f3f1d
author Jim Grosbach <grosbach@apple.com> Mon Oct 24 23:26:05 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Mon Oct 24 23:26:05 2011 +0000
tree b7f34c5ac70955d31453909a11cbbbee604c24d9
parent 171f485f159e094f1d0b1d87984a73d4e3eb2ffa

ARM assembly parsing and encoding for VLD1 w/ writeback.

Three entry register list variation.

llvm-svn: 142876

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d6b9260..ddc5c99 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2070,10 +2070,14 @@
     case ARM::VLD1q16wb_register:
     case ARM::VLD1q32wb_register:
     case ARM::VLD1q64wb_register:
-    case ARM::VLD1d8T_UPD:
-    case ARM::VLD1d16T_UPD:
-    case ARM::VLD1d32T_UPD:
-    case ARM::VLD1d64T_UPD:
+    case ARM::VLD1d8Twb_fixed:
+    case ARM::VLD1d8Twb_register:
+    case ARM::VLD1d16Twb_fixed:
+    case ARM::VLD1d16Twb_register:
+    case ARM::VLD1d32Twb_fixed:
+    case ARM::VLD1d32Twb_register:
+    case ARM::VLD1d64Twb_fixed:
+    case ARM::VLD1d64Twb_register:
     case ARM::VLD1d8Q_UPD:
     case ARM::VLD1d16Q_UPD:
     case ARM::VLD1d32Q_UPD: