commit 93dd77d2dcc581e2dcff49808fd7423a9b95d7aa
author Craig Topper <craig.topper@intel.com> Sun Mar 18 08:38:03 2018 +0000
committer Craig Topper <craig.topper@intel.com> Sun Mar 18 08:38:03 2018 +0000
tree b03c344236911a005552a0d50bd1cb56a45f29b8
parent 7f31e735c9791f005a39677add8e99584d75c7a5

[TableGen] Remove unnecessary uses of make_range.

llvm-svn: 327785

llvm/utils/TableGen/CodeGenSchedule.cpp

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 90ac856..59ea54f 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -746,7 +746,7 @@
   if (InstDefs->empty())
     PrintFatalError(InstRWDef->getLoc(), "No matching instruction opcodes");
 
-  for (Record *InstDef : make_range(InstDefs->begin(), InstDefs->end())) {
+  for (Record *InstDef : *InstDefs) {
     InstClassMapTy::const_iterator Pos = InstrClassMap.find(InstDef);
     if (Pos == InstrClassMap.end())
       PrintFatalError(InstDef->getLoc(), "No sched class for instruction.");
@@ -774,7 +774,7 @@
       if (!RWDefs.empty()) {
         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
         unsigned OrigNumInstrs = 0;
-        for (Record *OIDef : make_range(OrigInstDefs->begin(), OrigInstDefs->end())) {
+        for (Record *OIDef : *OrigInstDefs) {
           if (InstrClassMap[OIDef] == OldSCIdx)
             ++OrigNumInstrs;
         }