Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index adc203b..c984ee1 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -362,63 +362,72 @@
let Constraints = cstr;
}
-class PseudoInst<dag ops, string asm, list<dag> pattern>
+class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
: InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> {
- let OperandList = ops;
+ let OutOperandList = oops;
+ let InOperandList = iops;
let AsmString = asm;
let Pattern = pattern;
}
// Almost all ARM instructions are predicable.
-class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
+class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
string opc, string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now.
: InstARM<0, am, sz, im, cstr> {
- let OperandList = !con(oprnds, (ops pred:$p));
+ let OutOperandList = oops;
+ let InOperandList = !con(iops, (ops pred:$p));
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
-// Same as I except it can optionally modify CPSR.
-class sI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
+// Same as I except it can optionally modify CPSR. Note it's modeled as
+// an input operand since by default it's a zero register. It will
+// become an implicit def once it's "flipped".
+class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
string opc, string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now.
: InstARM<0, am, sz, im, cstr> {
- let OperandList = !con(oprnds, (ops pred:$p, cc_out:$s));
+ let OutOperandList = oops;
+ let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
-class AI<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AsI<dag ops, string opc, string asm, list<dag> pattern>
- : sI<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI1<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AsI1<dag ops, string opc, string asm, list<dag> pattern>
- : sI<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI2<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI3<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI4<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
-class AI1x2<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm,"",pattern>;
+class AsI<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, opc,asm,"",pattern>;
+class AI1<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AsI1<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AI2<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AI3<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AI4<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
+class AI1x2<dag oops, dag iops, string opc, string asm, list<dag> pattern>
+ : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
// Pre-indexed ops
-class AI2pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
- : I<ops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
-class AI3pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
- : I<ops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
+class AI2pr<dag oops, dag iops, string opc, string asm, string cstr,
+ list<dag> pattern>
+ : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
+class AI3pr<dag oops, dag iops, string opc, string asm, string cstr,
+ list<dag> pattern>
+ : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
// Post-indexed ops
-class AI2po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
- : I<ops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
-class AI3po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
- : I<ops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
+class AI2po<dag oops, dag iops, string opc, string asm, string cstr,
+ list<dag> pattern>
+ : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>;
+class AI3po<dag oops, dag iops, string opc, string asm, string cstr,
+ list<dag> pattern>
+ : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr,pattern>;
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
@@ -428,13 +437,13 @@
/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
/// binop that produces a value.
multiclass AsI1_bin_irs<string opc, PatFrag opnode> {
- def ri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
+ def ri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
- def rr : AsI1<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def rr : AsI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
- def rs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
+ def rs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
opc, " $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
}
@@ -442,13 +451,13 @@
/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
/// instruction modifies the CSPR register.
multiclass ASI1_bin_s_irs<string opc, PatFrag opnode> {
- def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
+ def ri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
- def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def rr : AI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>;
- def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
+ def rs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
opc, "s $dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>;
}
@@ -457,13 +466,13 @@
/// patterns. Similar to AsI1_bin_irs except the instruction does not produce
/// a explicit result, only implicitly set CPSR.
multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
- def ri : AI1<(ops GPR:$a, so_imm:$b),
+ def ri : AI1<(outs), (ins GPR:$a, so_imm:$b),
opc, " $a, $b",
[(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>;
- def rr : AI1<(ops GPR:$a, GPR:$b),
+ def rr : AI1<(outs), (ins GPR:$a, GPR:$b),
opc, " $a, $b",
[(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>;
- def rs : AI1<(ops GPR:$a, so_reg:$b),
+ def rs : AI1<(outs), (ins GPR:$a, so_reg:$b),
opc, " $a, $b",
[(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
}
@@ -471,10 +480,10 @@
/// AI_unary_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24.
multiclass AI_unary_rrot<string opc, PatFrag opnode> {
- def r : AI<(ops GPR:$dst, GPR:$Src),
+ def r : AI<(outs GPR:$dst), (ins GPR:$Src),
opc, " $dst, $Src",
[(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
- def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
+ def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
opc, " $dst, $Src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]>;
@@ -483,11 +492,11 @@
/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24.
multiclass AI_bin_rrot<string opc, PatFrag opnode> {
- def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
+ def rr : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
opc, " $dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
Requires<[IsARM, HasV6]>;
- def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
+ def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
opc, " $dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS,
(rotr GPR:$RHS, rot_imm:$rot)))]>,
@@ -495,48 +504,49 @@
}
// Special cases.
-class XI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
+class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im,
string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now.
: InstARM<0, am, sz, im, cstr> {
- let OperandList = oprnds;
+ let OutOperandList = oops;
+ let InOperandList = iops;
let AsmString = asm;
let Pattern = pattern;
list<Predicate> Predicates = [IsARM];
}
-class AXI<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI1<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI2<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI3<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXI4<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AXI<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AXI1<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AXI2<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AXI3<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
+class AXI4<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AXIx2<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
+class AXIx2<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
// BR_JT instructions
-class JTI<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
-class JTI1<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
-class JTI2<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
+class JTI<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
+class JTI1<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
+class JTI2<dag oops, dag iops, string asm, list<dag> pattern>
+ : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
/// setting carry bit. But it can optionally set CPSR.
multiclass AsXI1_bin_c_irs<string opc, PatFrag opnode> {
- def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s),
+ def ri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
!strconcat(opc, "${s} $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
- def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b, cc_out:$s),
+ def rr : AXI1<(outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
!strconcat(opc, "${s} $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
- def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s),
+ def rs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
!strconcat(opc, "${s} $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
}
@@ -549,7 +559,7 @@
// Miscellaneous Instructions.
//
def IMPLICIT_DEF_GPR :
-PseudoInst<(ops GPR:$rD, pred:$p),
+PseudoInst<(outs GPR:$rD), (ins pred:$p),
"@ IMPLICIT_DEF_GPR $rD",
[(set GPR:$rD, (undef))]>;
@@ -560,68 +570,69 @@
/// size in bytes of this constant pool entry.
let isNotDuplicable = 1 in
def CONSTPOOL_ENTRY :
-PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
+PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
+ i32imm:$size),
"${instid:label} ${cpidx:cpentry}", []>;
def ADJCALLSTACKUP :
-PseudoInst<(ops i32imm:$amt, pred:$p),
+PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
"@ ADJCALLSTACKUP $amt",
[(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
def ADJCALLSTACKDOWN :
-PseudoInst<(ops i32imm:$amt, pred:$p),
+PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
"@ ADJCALLSTACKDOWN $amt",
[(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
def DWARF_LOC :
-PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
+PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
let isNotDuplicable = 1 in {
-def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p),
+def PICADD : AXI1<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
"$cp:\n\tadd$p $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
let isLoad = 1, AddedComplexity = 10 in {
-def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLD : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
-def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDZH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
-def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDZB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
-def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
-def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDB : AXI2<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
-def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDSH : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr${p}sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
-def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
+def PICLDSB : AXI3<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
}
let isStore = 1, AddedComplexity = 10 in {
-def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTR : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>;
-def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTRH : AXI3<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tstr${p}h $src, $addr",
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
-def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
+def PICSTRB : AXI2<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
"${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
}
@@ -632,34 +643,37 @@
//
let isReturn = 1, isTerminator = 1 in
- def BX_RET : AI<(ops), "bx", " lr", [(ARMretflag)]>;
+ def BX_RET : AI<(outs), (ins), "bx", " lr", [(ARMretflag)]>;
// FIXME: remove when we have a way to marking a MI with these properties.
+// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
+// operand list.
let isLoad = 1, isReturn = 1, isTerminator = 1 in
- def LDM_RET : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
+ def LDM_RET : AXI4<(outs),
+ (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
"ldm${p}${addr:submode} $addr, $dst1",
[]>;
let isCall = 1, noResults = 1,
Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
- def BL : AXI<(ops i32imm:$func, variable_ops),
+ def BL : AXI<(outs), (ins i32imm:$func, variable_ops),
"bl ${func:call}",
[(ARMcall tglobaladdr:$func)]>;
- def BL_pred : AI<(ops i32imm:$func, variable_ops),
+ def BL_pred : AI<(outs), (ins i32imm:$func, variable_ops),
"bl", " ${func:call}",
[(ARMcall_pred tglobaladdr:$func)]>;
// ARMv5T and above
- def BLX : AXI<(ops GPR:$dst, variable_ops),
- "blx $dst",
- [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
+ def BLX : AXI<(outs), (ins GPR:$func, variable_ops),
+ "blx $func",
+ [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
let Uses = [LR] in {
// ARMv4T
- def BX : AXIx2<(ops GPR:$dst, variable_ops),
- "mov lr, pc\n\tbx $dst",
- [(ARMcall_nolink GPR:$dst)]>;
+ def BX : AXIx2<(outs), (ins GPR:$func, variable_ops),
+ "mov lr, pc\n\tbx $func",
+ [(ARMcall_nolink GPR:$func)]>;
}
}
@@ -667,28 +681,29 @@
// B is "predicable" since it can be xformed into a Bcc.
let isBarrier = 1 in {
let isPredicable = 1 in
- def B : AXI<(ops brtarget:$dst), "b $dst",
- [(br bb:$dst)]>;
+ def B : AXI<(outs), (ins brtarget:$target), "b $target",
+ [(br bb:$target)]>;
let isNotDuplicable = 1 in {
- def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
- "mov pc, $dst \n$jt",
- [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
- def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
- "ldr pc, $dst \n$jt",
- [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
+ def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
+ "mov pc, $target \n$jt",
+ [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
+ def BR_JTm : JTI2<(outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
+ "ldr pc, $target \n$jt",
+ [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
imm:$id)]>;
- def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
- "add pc, $dst, $idx \n$jt",
- [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
+ def BR_JTadd : JTI1<(outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
+ i32imm:$id),
+ "add pc, $target, $idx \n$jt",
+ [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
imm:$id)]>;
}
}
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
- def Bcc : AI<(ops brtarget:$dst), "b", " $dst",
- [/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
+ def Bcc : AI<(outs), (ins brtarget:$target), "b", " $target",
+ [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
}
//===----------------------------------------------------------------------===//
@@ -697,117 +712,123 @@
// Load
let isLoad = 1 in {
-def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
+def LDR : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
"ldr", " $dst, $addr",
[(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools.
let isReMaterializable = 1 in
-def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
+def LDRcp : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
"ldr", " $dst, $addr", []>;
// Loads with zero extension
-def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
+def LDRH : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
"ldr", "h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
-def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
+def LDRB : AI2<(outs GPR:$dst), (ins addrmode2:$addr),
"ldr", "b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
// Loads with sign extension
-def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
+def LDRSH : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
"ldr", "sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
-def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
+def LDRSB : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
"ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
// Load doubleword
-def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
+def LDRD : AI3<(outs GPR:$dst), (ins addrmode3:$addr),
"ldr", "d $dst, $addr",
[]>, Requires<[IsARM, HasV5T]>;
// Indexed loads
-def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
+def LDR_PRE : AI2pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode2:$addr),
"ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
+def LDR_POST : AI2po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base, am2offset:$offset),
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
+def LDRH_PRE : AI3pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode3:$addr),
"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
+def LDRH_POST : AI3po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am3offset:$offset),
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
+def LDRB_PRE : AI2pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode2:$addr),
"ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
+def LDRB_POST : AI2po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am2offset:$offset),
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
+def LDRSH_PRE : AI3pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode3:$addr),
"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
+def LDRSH_POST: AI3po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am3offset:$offset),
"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
-def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
+def LDRSB_PRE : AI3pr<(outs GPR:$dst), (ins GPR:$base_wb, addrmode3:$addr),
"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
-def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
+def LDRSB_POST: AI3po<(outs GPR:$dst), (ins GPR:$base_wb, GPR:$base,am3offset:$offset),
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
} // isLoad
// Store
let isStore = 1 in {
-def STR : AI2<(ops GPR:$src, addrmode2:$addr),
+def STR : AI2<(outs), (ins GPR:$src, addrmode2:$addr),
"str", " $src, $addr",
[(store GPR:$src, addrmode2:$addr)]>;
// Stores with truncate
-def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
+def STRH : AI3<(outs), (ins GPR:$src, addrmode3:$addr),
"str", "h $src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
-def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
+def STRB : AI2<(outs), (ins GPR:$src, addrmode2:$addr),
"str", "b $src, $addr",
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword
-def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
+def STRD : AI3<(outs), (ins GPR:$src, addrmode3:$addr),
"str", "d $src, $addr",
[]>, Requires<[IsARM, HasV5T]>;
// Indexed stores
-def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
+def STR_PRE : AI2pr<(outs GPR:$base_wb),
+ (ins GPR:$src, GPR:$base, am2offset:$offset),
"str", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
-def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
+def STR_POST : AI2po<(outs GPR:$base_wb),
+ (ins GPR:$src, GPR:$base,am2offset:$offset),
"str", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb,
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
-def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
+def STRH_PRE : AI3pr<(outs GPR:$base_wb),
+ (ins GPR:$src, GPR:$base,am3offset:$offset),
"str", "h $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
-def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
+def STRH_POST: AI3po<(outs GPR:$base_wb),
+ (ins GPR:$src, GPR:$base,am3offset:$offset),
"str", "h $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
GPR:$base, am3offset:$offset))]>;
-def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
+def STRB_PRE : AI2pr<(outs GPR:$base_wb),
+ (ins GPR:$src, GPR:$base,am2offset:$offset),
"str", "b $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>;
-def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
+def STRB_POST: AI2po<(outs GPR:$base_wb),
+ (ins GPR:$src, GPR:$base,am2offset:$offset),
"str", "b $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>;
@@ -817,13 +838,16 @@
// Load / store multiple Instructions.
//
+// FIXME: $dst1 should be a def.
let isLoad = 1 in
-def LDM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
+def LDM : AXI4<(outs),
+ (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
"ldm${p}${addr:submode} $addr, $dst1",
[]>;
let isStore = 1 in
-def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
+def STM : AXI4<(outs),
+ (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
"stm${p}${addr:submode} $addr, $src1",
[]>;
@@ -831,26 +855,26 @@
// Move Instructions.
//
-def MOVr : AsI1<(ops GPR:$dst, GPR:$src),
+def MOVr : AsI1<(outs GPR:$dst), (ins GPR:$src),
"mov", " $dst, $src", []>;
-def MOVs : AsI1<(ops GPR:$dst, so_reg:$src),
+def MOVs : AsI1<(outs GPR:$dst), (ins so_reg:$src),
"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
let isReMaterializable = 1 in
-def MOVi : AsI1<(ops GPR:$dst, so_imm:$src),
+def MOVi : AsI1<(outs GPR:$dst), (ins so_imm:$src),
"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
-def MOVrx : AsI1<(ops GPR:$dst, GPR:$src),
- "mov", " $dst, $src, rrx",
- [(set GPR:$dst, (ARMrrx GPR:$src))]>;
+def MOVrx : AsI1<(outs GPR:$dst), (ins GPR:$src),
+ "mov", " $dst, $src, rrx",
+ [(set GPR:$dst, (ARMrrx GPR:$src))]>;
// These aren't really mov instructions, but we have to define them this way
// due to flag operands.
-def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
+def MOVsrl_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
"mov", "s $dst, $src, lsr #1",
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
-def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
+def MOVsra_flag : AI1<(outs GPR:$dst), (ins GPR:$src),
"mov", "s $dst, $src, asr #1",
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
@@ -909,27 +933,27 @@
defm SBC : AsXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
// These don't define reg/reg forms, because they are handled above.
-def RSBri : AsI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
+def RSBri : AsI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
"rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
-def RSBrs : AsI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
+def RSBrs : AsI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
"rsb", " $dst, $a, $b",
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
// RSB with 's' bit set.
-def RSBSri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
+def RSBSri : AI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b),
"rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
-def RSBSrs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
+def RSBSrs : AI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b),
"rsb", "s $dst, $a, $b",
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
-def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b, cc_out:$s),
+def RSCri : AXI1<(outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
"rsc${s} $dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
-def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b, cc_out:$s),
+def RSCrs : AXI1<(outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
"rsc${s} $dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
@@ -958,12 +982,12 @@
defm EOR : AsI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
defm BIC : AsI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
-def MVNr : AsI<(ops GPR:$dst, GPR:$src),
+def MVNr : AsI<(outs GPR:$dst), (ins GPR:$src),
"mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
-def MVNs : AsI<(ops GPR:$dst, so_reg:$src),
+def MVNs : AsI<(outs GPR:$dst), (ins so_reg:$src),
"mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
let isReMaterializable = 1 in
-def MVNi : AsI<(ops GPR:$dst, so_imm:$imm),
+def MVNi : AsI<(outs GPR:$dst), (ins so_imm:$imm),
"mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
def : ARMPat<(and GPR:$src, so_imm_not:$imm),
@@ -973,76 +997,76 @@
// Multiply Instructions.
//
-def MUL : AsI<(ops GPR:$dst, GPR:$a, GPR:$b),
+def MUL : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
"mul", " $dst, $a, $b",
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
-def MLA : AsI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
+def MLA : AsI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
"mla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
// Extra precision multiplies with low / high results
-def SMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
+def SMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
"smull", " $ldst, $hdst, $a, $b", []>;
-def UMULL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
+def UMULL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
"umull", " $ldst, $hdst, $a, $b", []>;
// Multiply + accumulate
-def SMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
+def SMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
"smlal", " $ldst, $hdst, $a, $b", []>;
-def UMLAL : AsI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
+def UMLAL : AsI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
"umlal", " $ldst, $hdst, $a, $b", []>;
-def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
+def UMAAL : AI<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
"umaal", " $ldst, $hdst, $a, $b", []>,
Requires<[IsARM, HasV6]>;
// Most significant word multiply
-def SMMUL : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+def SMMUL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
"smmul", " $dst, $a, $b",
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
Requires<[IsARM, HasV6]>;
-def SMMLA : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
+def SMMLA : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
"smmla", " $dst, $a, $b, $c",
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
Requires<[IsARM, HasV6]>;
-def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
+def SMMLS : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
"smmls", " $dst, $a, $b, $c",
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
Requires<[IsARM, HasV6]>;
multiclass AI_smul<string opc, PatFrag opnode> {
- def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "bb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16)))]>,
Requires<[IsARM, HasV5TE]>;
- def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "bt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, 16)))]>,
Requires<[IsARM, HasV5TE]>;
- def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "tb"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, 16),
(sext_inreg GPR:$b, i16)))]>,
Requires<[IsARM, HasV5TE]>;
- def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "tt"), " $dst, $a, $b",
[(set GPR:$dst, (opnode (sra GPR:$a, 16),
(sra GPR:$b, 16)))]>,
Requires<[IsARM, HasV5TE]>;
- def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "wb"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), 16))]>,
Requires<[IsARM, HasV5TE]>;
- def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
+ def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
!strconcat(opc, "wt"), " $dst, $a, $b",
[(set GPR:$dst, (sra (opnode GPR:$a,
(sra GPR:$b, 16)), 16))]>,
@@ -1050,34 +1074,34 @@
}
multiclass AI_smla<string opc, PatFrag opnode> {
- def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
+ def BB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc,
(opnode (sext_inreg GPR:$a, i16),
(sext_inreg GPR:$b, i16))))]>,
Requires<[IsARM, HasV5TE]>;
- def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
+ def BT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "bt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
(sra GPR:$b, 16))))]>,
Requires<[IsARM, HasV5TE]>;
- def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
+ def TB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "tb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
(sext_inreg GPR:$b, i16))))]>,
Requires<[IsARM, HasV5TE]>;
- def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
+ def TT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "tt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
(sra GPR:$b, 16))))]>,
Requires<[IsARM, HasV5TE]>;
- def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
+ def WB : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "wb"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sext_inreg GPR:$b, i16)), 16)))]>,
Requires<[IsARM, HasV5TE]>;
- def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
+ def WT : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
!strconcat(opc, "wt"), " $dst, $a, $b, $acc",
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
(sra GPR:$b, 16)), 16)))]>,
@@ -1094,15 +1118,15 @@
// Misc. Arithmetic Instructions.
//
-def CLZ : AI<(ops GPR:$dst, GPR:$src),
+def CLZ : AI<(outs GPR:$dst), (ins GPR:$src),
"clz", " $dst, $src",
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
-def REV : AI<(ops GPR:$dst, GPR:$src),
+def REV : AI<(outs GPR:$dst), (ins GPR:$src),
"rev", " $dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
-def REV16 : AI<(ops GPR:$dst, GPR:$src),
+def REV16 : AI<(outs GPR:$dst), (ins GPR:$src),
"rev16", " $dst, $src",
[(set GPR:$dst,
(or (and (srl GPR:$src, 8), 0xFF),
@@ -1111,7 +1135,7 @@
(and (shl GPR:$src, 8), 0xFF000000)))))]>,
Requires<[IsARM, HasV6]>;
-def REVSH : AI<(ops GPR:$dst, GPR:$src),
+def REVSH : AI<(outs GPR:$dst), (ins GPR:$src),
"revsh", " $dst, $src",
[(set GPR:$dst,
(sext_inreg
@@ -1119,7 +1143,7 @@
(shl GPR:$src, 8)), i16))]>,
Requires<[IsARM, HasV6]>;
-def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
+def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
"pkhbt", " $dst, $src1, $src2, LSL $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
(and (shl GPR:$src2, (i32 imm:$shamt)),
@@ -1133,7 +1157,7 @@
(PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
-def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
+def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
"pkhtb", " $dst, $src1, $src2, ASR $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
(and (sra GPR:$src2, imm16_31:$shamt),
@@ -1172,17 +1196,17 @@
// Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
-def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true),
+def MOVCCr : AI<(outs GPR:$dst), (ins GPR:$false, GPR:$true),
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
-def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true),
+def MOVCCs : AI<(outs GPR:$dst), (ins GPR:$false, so_reg:$true),
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
-def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true),
+def MOVCCi : AI<(outs GPR:$dst), (ins GPR:$false, so_imm:$true),
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
@@ -1190,14 +1214,14 @@
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
-def LEApcrel : AXI1<(ops GPR:$dst, i32imm:$label, pred:$p),
+def LEApcrel : AXI1<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")),
[]>;
-def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
+def LEApcrelJT : AXI1<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
@@ -1211,7 +1235,7 @@
// __aeabi_read_tp preserves the registers r1-r3.
let isCall = 1,
Defs = [R0, R12, LR, CPSR] in {
- def TPsoft : AXI<(ops),
+ def TPsoft : AXI<(outs), (ins),
"bl __aeabi_read_tp",
[(set R0, ARMthread_pointer)]>;
}
@@ -1230,7 +1254,7 @@
// Two piece so_imms.
let isReMaterializable = 1 in
-def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
+def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
"mov", " $dst, $src",
[(set GPR:$dst, so_imm2part:$src)]>;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 27231da..757b876 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -29,38 +29,39 @@
list<Predicate> Predicates = [IsThumb, HasV5T];
}
-class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
+class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now.
: InstARM<0, am, sz, IndexModeNone, cstr> {
- let OperandList = ops;
+ let OutOperandList = outs;
+ let InOperandList = ins;
let AsmString = asm;
let Pattern = pattern;
list<Predicate> Predicates = [IsThumb];
}
-class TI<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
-class TI1<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
-class TI2<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
-class TI4<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
-class TIs<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
+class TI<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
+class TI1<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
+class TI2<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
+class TI4<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
+class TIs<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
// Two-address instructions
-class TIt<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
+class TIt<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
// BL, BLX(1) are translated by assembler into two instructions
-class TIx2<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
+class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
// BR_JT instructions
-class TJTI<dag ops, string asm, list<dag> pattern>
- : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
+class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
+ : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
def imm_neg_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
@@ -160,17 +161,17 @@
//
def tADJCALLSTACKUP :
-PseudoInst<(ops i32imm:$amt),
+PseudoInst<(outs), (ins i32imm:$amt),
"@ tADJCALLSTACKUP $amt",
[(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
def tADJCALLSTACKDOWN :
-PseudoInst<(ops i32imm:$amt),
+PseudoInst<(outs), (ins i32imm:$amt),
"@ tADJCALLSTACKDOWN $amt",
[(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
let isNotDuplicable = 1 in
-def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
+def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
"$cp:\n\tadd $dst, pc",
[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
@@ -179,120 +180,122 @@
//
let isReturn = 1, isTerminator = 1 in {
- def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
+ def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
// Alternative return instruction used by vararg functions.
- def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>;
+ def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>;
}
// FIXME: remove when we have a way to marking a MI with these properties.
let isLoad = 1, isReturn = 1, isTerminator = 1 in
-def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
+def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
let isCall = 1, noResults = 1,
Defs = [R0, R1, R2, R3, LR,
D0, D1, D2, D3, D4, D5, D6, D7] in {
- def tBL : TIx2<(ops i32imm:$func, variable_ops),
+ def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
"bl ${func:call}",
[(ARMtcall tglobaladdr:$func)]>;
// ARMv5T and above
- def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
+ def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
"blx ${func:call}",
[(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
- def tBLXr : TI<(ops GPR:$dst, variable_ops),
- "blx $dst",
- [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
+ def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
+ "blx $func",
+ [(ARMtcall GPR:$func)]>, Requires<[HasV5T]>;
// ARMv4T
- def tBX : TIx2<(ops GPR:$dst, variable_ops),
- "cpy lr, pc\n\tbx $dst",
- [(ARMcall_nolink GPR:$dst)]>;
+ def tBX : TIx2<(outs), (ins GPR:$func, variable_ops),
+ "cpy lr, pc\n\tbx $func",
+ [(ARMcall_nolink GPR:$func)]>;
}
let isBranch = 1, isTerminator = 1, noResults = 1 in {
let isBarrier = 1 in {
let isPredicable = 1 in
- def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
+ def tB : TI<(outs), (ins brtarget:$target), "b $target",
+ [(br bb:$target)]>;
// Far jump
- def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
+ def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
- def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
- "cpy pc, $dst \n\t.align\t2\n$jt",
- [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
+ def tBR_JTr : TJTI<(outs),
+ (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
+ "cpy pc, $target \n\t.align\t2\n$jt",
+ [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
}
}
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1, noResults = 1 in
- def tBcc : TI<(ops brtarget:$dst, pred:$cc), "b$cc $dst",
- [/*(ARMbrcond bb:$dst, imm:$cc)*/]>;
+ def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
+ [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
//===----------------------------------------------------------------------===//
// Load Store Instructions.
//
let isLoad = 1 in {
-def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
+def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
-def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
+def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr),
"ldrb $dst, $addr",
[(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
-def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
+def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr),
"ldrh $dst, $addr",
[(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
-def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
+def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
"ldrsb $dst, $addr",
[(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
-def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
+def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
"ldrsh $dst, $addr",
[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
-def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
+def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
// Special instruction for restore. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
-def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
+def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
"ldr $dst, $addr", []>;
// Load tconstpool
-def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
+def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr",
[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools.
let isReMaterializable = 1 in
-def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
+def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
"ldr $dst, $addr", []>;
} // isLoad
let isStore = 1 in {
-def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
+def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
"str $src, $addr",
[(store GPR:$src, t_addrmode_s4:$addr)]>;
-def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
+def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr),
"strb $src, $addr",
[(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
-def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
+def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr),
"strh $src, $addr",
[(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
-def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
+def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
"str $src, $addr",
[(store GPR:$src, t_addrmode_sp:$addr)]>;
// Special instruction for spill. It cannot clobber condition register
// when it's expanded by eliminateCallFramePseudoInstr().
-def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
+def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
"str $src, $addr", []>;
}
@@ -303,11 +306,11 @@
// TODO: A7-44: LDMIA - load multiple
let isLoad = 1 in
-def tPOP : TI<(ops reglist:$dst1, variable_ops),
+def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
let isStore = 1 in
-def tPUSH : TI<(ops reglist:$src1, variable_ops),
+def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
"push $src1", []>;
//===----------------------------------------------------------------------===//
@@ -315,106 +318,106 @@
//
// Add with carry
-def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"adc $dst, $rhs",
[(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
-def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"add $dst, $lhs, $rhs",
[(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
-def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"add $dst, $lhs, $rhs",
[(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
-def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"add $dst, $rhs",
[(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
-def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"add $dst, $lhs, $rhs",
[(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
-def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"add $dst, $rhs", []>;
-def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
+def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs),
"add $dst, pc, $rhs * 4", []>;
-def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
+def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs),
"add $dst, $sp, $rhs * 4", []>;
-def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"add $dst, $rhs * 4", []>;
-def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"and $dst, $rhs",
[(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
-def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"asr $dst, $lhs, $rhs",
[(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
-def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"asr $dst, $rhs",
[(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
-def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"bic $dst, $rhs",
[(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
-def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
+def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
"cmn $lhs, $rhs",
[(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
-def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
+def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
"cmp $lhs, $rhs",
[(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
-def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
+def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
"cmp $lhs, $rhs",
[(ARMcmp GPR:$lhs, GPR:$rhs)]>;
-def tTST : TI<(ops GPR:$lhs, GPR:$rhs),
+def tTST : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
"tst $lhs, $rhs",
[(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
-def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs),
+def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
"cmn $lhs, $rhs",
[(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
-def tCMPNZi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
+def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
"cmp $lhs, $rhs",
[(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
-def tCMPNZr : TI<(ops GPR:$lhs, GPR:$rhs),
+def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
"cmp $lhs, $rhs",
[(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
// TODO: A7-37: CMP(3) - cmp hi regs
-def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"eor $dst, $rhs",
[(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
-def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"lsl $dst, $lhs, $rhs",
[(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
-def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"lsl $dst, $rhs",
[(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
-def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"lsr $dst, $lhs, $rhs",
[(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
-def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"lsr $dst, $rhs",
[(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
// FIXME: This is not rematerializable because mov changes the condition code.
-def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
+def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src),
"mov $dst, $src",
[(set GPR:$dst, imm0_255:$src)]>;
@@ -423,32 +426,32 @@
// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
// which is MOV(3). This also supports high registers.
-def tMOVr : TI<(ops GPR:$dst, GPR:$src),
+def tMOVr : TI<(outs GPR:$dst), (ins GPR:$src),
"cpy $dst, $src", []>;
-def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"mul $dst, $rhs",
[(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
-def tMVN : TI<(ops GPR:$dst, GPR:$src),
+def tMVN : TI<(outs GPR:$dst), (ins GPR:$src),
"mvn $dst, $src",
[(set GPR:$dst, (not GPR:$src))]>;
-def tNEG : TI<(ops GPR:$dst, GPR:$src),
+def tNEG : TI<(outs GPR:$dst), (ins GPR:$src),
"neg $dst, $src",
[(set GPR:$dst, (ineg GPR:$src))]>;
-def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"orr $dst, $rhs",
[(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
-def tREV : TI<(ops GPR:$dst, GPR:$src),
+def tREV : TI<(outs GPR:$dst), (ins GPR:$src),
"rev $dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>,
Requires<[IsThumb, HasV6]>;
-def tREV16 : TI<(ops GPR:$dst, GPR:$src),
+def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src),
"rev16 $dst, $src",
[(set GPR:$dst,
(or (and (srl GPR:$src, 8), 0xFF),
@@ -457,7 +460,7 @@
(and (shl GPR:$src, 8), 0xFF000000)))))]>,
Requires<[IsThumb, HasV6]>;
-def tREVSH : TI<(ops GPR:$dst, GPR:$src),
+def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src),
"revsh $dst, $src",
[(set GPR:$dst,
(sext_inreg
@@ -465,53 +468,53 @@
(shl GPR:$src, 8)), i16))]>,
Requires<[IsThumb, HasV6]>;
-def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"ror $dst, $rhs",
[(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
// Subtract with carry
-def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"sbc $dst, $rhs",
[(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
-def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"sub $dst, $lhs, $rhs",
[(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
// TODO: A7-96: STMIA - store multiple.
-def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"sub $dst, $lhs, $rhs",
[(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
-def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"sub $dst, $rhs",
[(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
-def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
+def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
"sub $dst, $lhs, $rhs",
[(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
-def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
"sub $dst, $rhs * 4", []>;
-def tSXTB : TI<(ops GPR:$dst, GPR:$src),
+def tSXTB : TI<(outs GPR:$dst), (ins GPR:$src),
"sxtb $dst, $src",
[(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
Requires<[IsThumb, HasV6]>;
-def tSXTH : TI<(ops GPR:$dst, GPR:$src),
+def tSXTH : TI<(outs GPR:$dst), (ins GPR:$src),
"sxth $dst, $src",
[(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
Requires<[IsThumb, HasV6]>;
-def tUXTB : TI<(ops GPR:$dst, GPR:$src),
+def tUXTB : TI<(outs GPR:$dst), (ins GPR:$src),
"uxtb $dst, $src",
[(set GPR:$dst, (and GPR:$src, 0xFF))]>,
Requires<[IsThumb, HasV6]>;
-def tUXTH : TI<(ops GPR:$dst, GPR:$src),
+def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src),
"uxth $dst, $src",
[(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
Requires<[IsThumb, HasV6]>;
@@ -521,20 +524,20 @@
// Expanded by the scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
def tMOVCCr :
- PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, pred:$cc),
+ PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc),
"@ tMOVCCr $cc",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
-def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
+def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label),
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
-def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
+def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id),
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
@@ -548,7 +551,7 @@
// __aeabi_read_tp preserves the registers r1-r3.
let isCall = 1,
Defs = [R0, LR] in {
- def tTPsoft : TIx2<(ops),
+ def tTPsoft : TIx2<(outs), (ins),
"bl __aeabi_read_tp",
[(set R0, ARMthread_pointer)]>;
}
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 4bb9f04..c89c964 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -16,45 +16,45 @@
//
// ARM Float Instruction
-class ASI<dag ops, string opc, string asm, list<dag> pattern>
- : AI<ops, opc, asm, pattern> {
+class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
+ : AI<outs, ins, opc, asm, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
-class ASI5<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> {
+class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
+ : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
// ARM Double Instruction
-class ADI<dag ops, string opc, string asm, list<dag> pattern>
- : AI<ops, opc, asm, pattern> {
+class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
+ : AI<outs, ins, opc, asm, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
-class ADI5<dag ops, string opc, string asm, list<dag> pattern>
- : I<ops, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> {
+class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
+ : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, opc, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
// Special cases.
-class AXSI<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> {
+class AXSI<dag outs, dag ins, string asm, list<dag> pattern>
+ : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
-class AXSI5<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
+class AXSI5<dag outs, dag ins, string asm, list<dag> pattern>
+ : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
-class AXDI<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> {
+class AXDI<dag outs, dag ins, string asm, list<dag> pattern>
+ : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
-class AXDI5<dag ops, string asm, list<dag> pattern>
- : XI<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
+class AXDI5<dag outs, dag ins, string asm, list<dag> pattern>
+ : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
}
@@ -83,21 +83,21 @@
//
let isLoad = 1 in {
-def FLDD : ADI5<(ops DPR:$dst, addrmode5:$addr),
+def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr),
"fldd", " $dst, $addr",
[(set DPR:$dst, (load addrmode5:$addr))]>;
-def FLDS : ASI5<(ops SPR:$dst, addrmode5:$addr),
+def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr),
"flds", " $dst, $addr",
[(set SPR:$dst, (load addrmode5:$addr))]>;
} // isLoad
let isStore = 1 in {
-def FSTD : ADI5<(ops DPR:$src, addrmode5:$addr),
+def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
"fstd", " $src, $addr",
[(store DPR:$src, addrmode5:$addr)]>;
-def FSTS : ASI5<(ops SPR:$src, addrmode5:$addr),
+def FSTS : ASI5<(outs), (ins SPR:$src, addrmode5:$addr),
"fsts", " $src, $addr",
[(store SPR:$src, addrmode5:$addr)]>;
} // isStore
@@ -107,21 +107,25 @@
//
let isLoad = 1 in {
-def FLDMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
+def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
+ variable_ops),
"fldm${addr:submode}d${p} ${addr:base}, $dst1",
[]>;
-def FLDMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops),
+def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
+ variable_ops),
"fldm${addr:submode}s${p} ${addr:base}, $dst1",
[]>;
} // isLoad
let isStore = 1 in {
-def FSTMD : AXDI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
+def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
+ variable_ops),
"fstm${addr:submode}d${p} ${addr:base}, $src1",
[]>;
-def FSTMS : AXSI5<(ops addrmode5:$addr, pred:$p, reglist:$src1, variable_ops),
+def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
+ variable_ops),
"fstm${addr:submode}s${p} ${addr:base}, $src1",
[]>;
} // isStore
@@ -132,43 +136,43 @@
// FP Binary Operations.
//
-def FADDD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
+def FADDD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
"faddd", " $dst, $a, $b",
[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
-def FADDS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
+def FADDS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
"fadds", " $dst, $a, $b",
[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
-def FCMPED : ADI<(ops DPR:$a, DPR:$b),
+def FCMPED : ADI<(outs), (ins DPR:$a, DPR:$b),
"fcmped", " $a, $b",
[(arm_cmpfp DPR:$a, DPR:$b)]>;
-def FCMPES : ASI<(ops SPR:$a, SPR:$b),
+def FCMPES : ASI<(outs), (ins SPR:$a, SPR:$b),
"fcmpes", " $a, $b",
[(arm_cmpfp SPR:$a, SPR:$b)]>;
-def FDIVD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
+def FDIVD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
"fdivd", " $dst, $a, $b",
[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
-def FDIVS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
+def FDIVS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
"fdivs", " $dst, $a, $b",
[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
-def FMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
+def FMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
"fmuld", " $dst, $a, $b",
[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
-def FMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
+def FMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
"fmuls", " $dst, $a, $b",
[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
-def FNMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
+def FNMULD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
"fnmuld", " $dst, $a, $b",
[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
-def FNMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
+def FNMULS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
"fnmuls", " $dst, $a, $b",
[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
@@ -179,11 +183,11 @@
(FNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
-def FSUBD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
+def FSUBD : ADI<(outs DPR:$dst), (ins DPR:$a, DPR:$b),
"fsubd", " $dst, $a, $b",
[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
-def FSUBS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
+def FSUBS : ASI<(outs SPR:$dst), (ins SPR:$a, SPR:$b),
"fsubs", " $dst, $a, $b",
[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
@@ -191,49 +195,49 @@
// FP Unary Operations.
//
-def FABSD : ADI<(ops DPR:$dst, DPR:$a),
+def FABSD : ADI<(outs DPR:$dst), (ins DPR:$a),
"fabsd", " $dst, $a",
[(set DPR:$dst, (fabs DPR:$a))]>;
-def FABSS : ASI<(ops SPR:$dst, SPR:$a),
+def FABSS : ASI<(outs SPR:$dst), (ins SPR:$a),
"fabss", " $dst, $a",
[(set SPR:$dst, (fabs SPR:$a))]>;
-def FCMPEZD : ADI<(ops DPR:$a),
+def FCMPEZD : ADI<(outs), (ins DPR:$a),
"fcmpezd", " $a",
[(arm_cmpfp0 DPR:$a)]>;
-def FCMPEZS : ASI<(ops SPR:$a),
+def FCMPEZS : ASI<(outs), (ins SPR:$a),
"fcmpezs", " $a",
[(arm_cmpfp0 SPR:$a)]>;
-def FCVTDS : ADI<(ops DPR:$dst, SPR:$a),
+def FCVTDS : ADI<(outs DPR:$dst), (ins SPR:$a),
"fcvtds", " $dst, $a",
[(set DPR:$dst, (fextend SPR:$a))]>;
-def FCVTSD : ADI<(ops SPR:$dst, DPR:$a),
+def FCVTSD : ADI<(outs SPR:$dst), (ins DPR:$a),
"fcvtsd", " $dst, $a",
[(set SPR:$dst, (fround DPR:$a))]>;
-def FCPYD : ADI<(ops DPR:$dst, DPR:$a),
+def FCPYD : ADI<(outs DPR:$dst), (ins DPR:$a),
"fcpyd", " $dst, $a", []>;
-def FCPYS : ASI<(ops SPR:$dst, SPR:$a),
+def FCPYS : ASI<(outs SPR:$dst), (ins SPR:$a),
"fcpys", " $dst, $a", []>;
-def FNEGD : ADI<(ops DPR:$dst, DPR:$a),
+def FNEGD : ADI<(outs DPR:$dst), (ins DPR:$a),
"fnegd", " $dst, $a",
[(set DPR:$dst, (fneg DPR:$a))]>;
-def FNEGS : ASI<(ops SPR:$dst, SPR:$a),
+def FNEGS : ASI<(outs SPR:$dst), (ins SPR:$a),
"fnegs", " $dst, $a",
[(set SPR:$dst, (fneg SPR:$a))]>;
-def FSQRTD : ADI<(ops DPR:$dst, DPR:$a),
+def FSQRTD : ADI<(outs DPR:$dst), (ins DPR:$a),
"fsqrtd", " $dst, $a",
[(set DPR:$dst, (fsqrt DPR:$a))]>;
-def FSQRTS : ASI<(ops SPR:$dst, SPR:$a),
+def FSQRTS : ASI<(outs SPR:$dst), (ins SPR:$a),
"fsqrts", " $dst, $a",
[(set SPR:$dst, (fsqrt SPR:$a))]>;
@@ -241,30 +245,30 @@
// FP <-> GPR Copies. Int <-> FP Conversions.
//
-def IMPLICIT_DEF_SPR : PseudoInst<(ops SPR:$rD, pred:$p),
+def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p),
"@ IMPLICIT_DEF_SPR $rD",
[(set SPR:$rD, (undef))]>;
-def IMPLICIT_DEF_DPR : PseudoInst<(ops DPR:$rD, pred:$p),
+def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p),
"@ IMPLICIT_DEF_DPR $rD",
[(set DPR:$rD, (undef))]>;
-def FMRS : ASI<(ops GPR:$dst, SPR:$src),
+def FMRS : ASI<(outs GPR:$dst), (ins SPR:$src),
"fmrs", " $dst, $src",
[(set GPR:$dst, (bitconvert SPR:$src))]>;
-def FMSR : ASI<(ops SPR:$dst, GPR:$src),
+def FMSR : ASI<(outs SPR:$dst), (ins GPR:$src),
"fmsr", " $dst, $src",
[(set SPR:$dst, (bitconvert GPR:$src))]>;
-def FMRRD : ADI<(ops GPR:$dst1, GPR:$dst2, DPR:$src),
+def FMRRD : ADI<(outs GPR:$dst1, GPR:$dst2), (ins DPR:$src),
"fmrrd", " $dst1, $dst2, $src",
[/* FIXME: Can't write pattern for multiple result instr*/]>;
// FMDHR: GPR -> SPR
// FMDLR: GPR -> SPR
-def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2),
+def FMDRR : ADI<(outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
"fmdrr", " $dst, $src1, $src2",
[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
@@ -275,45 +279,45 @@
// FMSRR: GPR -> SPR
-def FMSTAT : ASI<(ops), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>;
+def FMSTAT : ASI<(outs), (ins), "fmstat", "", [(arm_fmstat)]>, Imp<[], [CPSR]>;
// FMXR: GPR -> VFP Sstem reg
// Int to FP:
-def FSITOD : ADI<(ops DPR:$dst, SPR:$a),
+def FSITOD : ADI<(outs DPR:$dst), (ins SPR:$a),
"fsitod", " $dst, $a",
[(set DPR:$dst, (arm_sitof SPR:$a))]>;
-def FSITOS : ASI<(ops SPR:$dst, SPR:$a),
+def FSITOS : ASI<(outs SPR:$dst), (ins SPR:$a),
"fsitos", " $dst, $a",
[(set SPR:$dst, (arm_sitof SPR:$a))]>;
-def FUITOD : ADI<(ops DPR:$dst, SPR:$a),
+def FUITOD : ADI<(outs DPR:$dst), (ins SPR:$a),
"fuitod", " $dst, $a",
[(set DPR:$dst, (arm_uitof SPR:$a))]>;
-def FUITOS : ASI<(ops SPR:$dst, SPR:$a),
+def FUITOS : ASI<(outs SPR:$dst), (ins SPR:$a),
"fuitos", " $dst, $a",
[(set SPR:$dst, (arm_uitof SPR:$a))]>;
// FP to Int:
// Always set Z bit in the instruction, i.e. "round towards zero" variants.
-def FTOSIZD : ADI<(ops SPR:$dst, DPR:$a),
+def FTOSIZD : ADI<(outs SPR:$dst), (ins DPR:$a),
"ftosizd", " $dst, $a",
[(set SPR:$dst, (arm_ftosi DPR:$a))]>;
-def FTOSIZS : ASI<(ops SPR:$dst, SPR:$a),
+def FTOSIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
"ftosizs", " $dst, $a",
[(set SPR:$dst, (arm_ftosi SPR:$a))]>;
-def FTOUIZD : ADI<(ops SPR:$dst, DPR:$a),
+def FTOUIZD : ADI<(outs SPR:$dst), (ins DPR:$a),
"ftouizd", " $dst, $a",
[(set SPR:$dst, (arm_ftoui DPR:$a))]>;
-def FTOUIZS : ASI<(ops SPR:$dst, SPR:$a),
+def FTOUIZS : ASI<(outs SPR:$dst), (ins SPR:$a),
"ftouizs", " $dst, $a",
[(set SPR:$dst, (arm_ftoui SPR:$a))]>;
@@ -321,42 +325,42 @@
// FP FMA Operations.
//
-def FMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
+def FMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
"fmacd", " $dst, $a, $b",
[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
+def FMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
"fmacs", " $dst, $a, $b",
[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
+def FMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
"fmscd", " $dst, $a, $b",
[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
+def FMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
"fmscs", " $dst, $a, $b",
[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FNMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
+def FNMACD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
"fnmacd", " $dst, $a, $b",
[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FNMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
+def FNMACS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
"fnmacs", " $dst, $a, $b",
[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FNMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
+def FNMSCD : ADI<(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
"fnmscd", " $dst, $a, $b",
[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
-def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
+def FNMSCS : ASI<(outs SPR:$dst), (ins SPR:$dstin, SPR:$a, SPR:$b),
"fnmscs", " $dst, $a, $b",
[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
RegConstraint<"$dstin = $dst">;
@@ -365,22 +369,22 @@
// FP Conditional moves.
//
-def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true),
+def FCPYDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true),
"fcpyd", " $dst, $true",
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
-def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true),
+def FCPYScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true),
"fcpys", " $dst, $true",
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
-def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true),
+def FNEGDcc : ADI<(outs DPR:$dst), (ins DPR:$false, DPR:$true),
"fnegd", " $dst, $true",
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
-def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true),
+def FNEGScc : ASI<(outs SPR:$dst), (ins SPR:$false, SPR:$true),
"fnegs", " $dst, $true",
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index f9d9342..eda31b0 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -327,8 +327,8 @@
return NewMI;
}
-const unsigned* ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
- const {
+const unsigned*
+ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
static const unsigned CalleeSavedRegs[] = {
ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
ARM::R7, ARM::R6, ARM::R5, ARM::R4,
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.h b/llvm/lib/Target/ARM/ARMRegisterInfo.h
index 3db1d89..a425bb6 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.h
@@ -68,8 +68,8 @@
const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
- const TargetRegisterClass* const* getCalleeSavedRegClasses(
- const MachineFunction *MF = 0) const;
+ const TargetRegisterClass* const*
+ getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
BitVector getReservedRegs(const MachineFunction &MF) const;