commit 954a012b4c75db77b99b259d9cc4edd8ab551c68
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Aug 21 16:59:10 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Aug 21 16:59:10 2019 +0000
tree 84f20d2ce1dc75c59cd1da8537abf315e35e07f5
parent 3c4614ff10e2a88d8ae800b0fb5746a686170c18

GlobalISel: Implement moreElementsVector for G_UNMERGE_VALUES sources

This is necessary for handling <3 x s16> on AMDGPU, assuming this
should be handled as 2 separate legalization actions. The alternative
would be for fewerElementsVector to handle 3->2.

llvm-svn: 369547

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 840aa0a..0fc7981 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -737,7 +737,7 @@
       // valid.
       .clampScalar(LitTyIdx, S16, S256)
       .widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)
-      .legalIf(all(typeIs(0, S16), typeIs(1, LLT::vector(3, 16)))) // FIXME: Testing hack
+      .moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
       .fewerElementsIf(all(typeIs(0, S16), vectorWiderThan(1, 32),
                            elementTypeIs(1, S16)),
                        changeTo(1, V2S16))