commit 95546b46ab62e8349346a0d0587eee8248dd4b2f
author Matt Arsenault <Matthew.Arsenault@amd.com> Sat Feb 14 02:55:57 2015 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Sat Feb 14 02:55:57 2015 +0000
tree 7712da20fe5da482bb9d8c62b204322caff998b5
parent 99981689821ea1fe41c06613f58110d4413a702f

R600/SI: Fix phys reg copies in SIFoldOperands

llvm-svn: 229227

llvm/lib/Target/R600/SIFoldOperands.cpp

diff --git a/llvm/lib/Target/R600/SIFoldOperands.cpp b/llvm/lib/Target/R600/SIFoldOperands.cpp
index 848638f..a1feeb4 100644
--- a/llvm/lib/Target/R600/SIFoldOperands.cpp
+++ b/llvm/lib/Target/R600/SIFoldOperands.cpp
@@ -210,7 +210,12 @@
         APInt Imm;
 
         if (FoldingImm) {
-          const TargetRegisterClass *UseRC = MRI.getRegClass(UseOp.getReg());
+          unsigned UseReg = UseOp.getReg();
+          const TargetRegisterClass *UseRC
+            = TargetRegisterInfo::isVirtualRegister(UseReg) ?
+            MRI.getRegClass(UseReg) :
+            TRI.getRegClass(UseReg);
+
           Imm = APInt(64, OpToFold.getImm());
 
           // Split 64-bit constants into 32-bits for folding.
@@ -229,8 +234,13 @@
           // In order to fold immediates into copies, we need to change the
           // copy to a MOV.
           if (UseMI->getOpcode() == AMDGPU::COPY) {
-            unsigned MovOp = TII->getMovOpcode(
-                MRI.getRegClass(UseMI->getOperand(0).getReg()));
+            unsigned DestReg = UseMI->getOperand(0).getReg();
+            const TargetRegisterClass *DestRC
+              = TargetRegisterInfo::isVirtualRegister(DestReg) ?
+              MRI.getRegClass(DestReg) :
+              TRI.getRegClass(DestReg);
+
+            unsigned MovOp = TII->getMovOpcode(DestRC);
             if (MovOp == AMDGPU::COPY)
               continue;