[InstCombine] Add constant vector support for X udiv C, where C >= signbit
llvm-svn: 324728
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index a5c6b97..b9d8e8f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -1067,8 +1067,7 @@
// X udiv C, where C >= signbit
static Instruction *foldUDivNegCst(Value *Op0, Value *Op1,
const BinaryOperator &I, InstCombiner &IC) {
- Value *ICI = IC.Builder.CreateICmpULT(Op0, cast<ConstantInt>(Op1));
-
+ Value *ICI = IC.Builder.CreateICmpULT(Op0, cast<Constant>(Op1));
return SelectInst::Create(ICI, Constant::getNullValue(I.getType()),
ConstantInt::get(I.getType(), 1));
}
@@ -1111,12 +1110,11 @@
return Actions.size();
}
- if (ConstantInt *C = dyn_cast<ConstantInt>(Op1))
- // X udiv C, where C >= signbit
- if (C->getValue().isNegative()) {
- Actions.push_back(UDivFoldAction(foldUDivNegCst, C));
- return Actions.size();
- }
+ // X udiv C, where C >= signbit
+ if (match(Op1, m_Negative())) {
+ Actions.push_back(UDivFoldAction(foldUDivNegCst, Op1));
+ return Actions.size();
+ }
// X udiv (C1 << N), where C1 is "1<<C2" --> X >> (N+C2)
if (match(Op1, m_Shl(m_Power2(), m_Value())) ||
diff --git a/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll b/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
index cae0155..0996fd5 100644
--- a/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
+++ b/llvm/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
@@ -24,7 +24,8 @@
define <2 x i32> @PR34856(<2 x i32> %t0, <2 x i32> %t1) {
; CHECK-LABEL: @PR34856(
-; CHECK-NEXT: [[DIV1:%.*]] = udiv <2 x i32> [[T1:%.*]], <i32 -7, i32 -7>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i32> [[T1:%.*]], <i32 -8, i32 -8>
+; CHECK-NEXT: [[DIV1:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[DIV1]]
;
%cmp = icmp eq <2 x i32> %t0, <i32 1, i32 1>
diff --git a/llvm/test/Transforms/InstCombine/vector-udiv.ll b/llvm/test/Transforms/InstCombine/vector-udiv.ll
index 58d2fec..e16c932 100644
--- a/llvm/test/Transforms/InstCombine/vector-udiv.ll
+++ b/llvm/test/Transforms/InstCombine/vector-udiv.ll
@@ -22,8 +22,9 @@
; X udiv C, where C >= signbit
define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_negconstsplat(
-; CHECK-NEXT: [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -3, i32 -3, i32 -3>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -4, i32 -4, i32 -4>
+; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%1 = udiv <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
ret <4 x i32> %1
@@ -31,8 +32,9 @@
define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_negconst(
-; CHECK-NEXT: [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9>
-; CHECK-NEXT: ret <4 x i32> [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -6, i32 -8, i32 -10>
+; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
ret <4 x i32> %1