commit 96b14e18bbbb0a8f649ef283893e4ad93dcfa5cb
author Chris Lattner <sabre@nondot.org> Thu Dec 02 17:57:21 2004 +0000
committer Chris Lattner <sabre@nondot.org> Thu Dec 02 17:57:21 2004 +0000
tree 531f21da96505c64059ba06cf92fc9048e5c4f34
parent fa83510f94491a7e65542c4b9322db25978596ae

Consider 64-bit registers to be FP as well.

llvm-svn: 18432

llvm/lib/Target/X86/X86ISelSimple.cpp

diff --git a/llvm/lib/Target/X86/X86ISelSimple.cpp b/llvm/lib/Target/X86/X86ISelSimple.cpp
index 89842a4..b1336f7 100644
--- a/llvm/lib/Target/X86/X86ISelSimple.cpp
+++ b/llvm/lib/Target/X86/X86ISelSimple.cpp
@@ -815,7 +815,9 @@
       MachineBasicBlock *SBB = *SI;
       for (MachineBasicBlock::iterator I = SBB->begin();
            I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
-        if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
+        const TargetRegisterClass *RC =
+          RegMap.getRegClass(I->getOperand(0).getReg());
+        if (RC->getSize() == 10 || RC->getSize() == 8)
           goto UsesFPReg;
       }
     }