commit 9706496b0d08d1a2ab6ccce1af6857cf4e5533df
author Andrew Trick <atrick@apple.com> Thu Jul 25 07:26:26 2013 +0000
committer Andrew Trick <atrick@apple.com> Thu Jul 25 07:26:26 2013 +0000
tree 2eba35a4946bb746c6e0e2256e59a7ead3ab6a44
parent e1fb94306decd4dfffeb3d03f0273971fded0ef3

Dump LIS before regalloc. MI sched changes them.

llvm-svn: 187107

llvm/lib/CodeGen/MachineScheduler.cpp

diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 2ee8775..19e86d7 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -204,7 +204,7 @@
   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 
   if (VerifyScheduling) {
-    DEBUG(LIS->print(dbgs()));
+    DEBUG(LIS->dump());
     MF->verify(this, "Before machine scheduling.");
   }
   RegClassInfo->runOnMachineFunction(*MF);
@@ -294,7 +294,7 @@
     Scheduler->finishBlock();
   }
   Scheduler->finalizeSchedule();
-  DEBUG(LIS->print(dbgs()));
+  DEBUG(LIS->dump());
   if (VerifyScheduling)
     MF->verify(this, "After machine scheduling.");
   return true;