[SystemZ] Add definitions for BRCT and BRCTG
llvm-svn: 187721
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 9883714..534ed88 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -489,6 +489,12 @@
// Inherent:
// One register output operand and no input operands.
//
+// BranchUnary:
+// One register output operand, one register input operand and
+// one branch displacement. The instructions stores a modified
+// form of the source register in the destination register and
+// branches on the result.
+//
// Store:
// One register or immediate input operand and one address input operand.
// The instruction stores the first operand to the address.
@@ -555,6 +561,15 @@
let R2 = 0;
}
+class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
+ : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
+ mnemonic##"\t$R1, $I2", []> {
+ let isBranch = 1;
+ let isTerminator = 1;
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {