| commit | 9797989ca745518577a0fdef684cbdb642ea4df0 | [log] [tgz] |
|---|---|---|
| author | Javed Absar <javed.absar@arm.com> | Fri Oct 07 13:41:55 2016 +0000 |
| committer | Javed Absar <javed.absar@arm.com> | Fri Oct 07 13:41:55 2016 +0000 |
| tree | 55327f8bafde52c9c222abe3e714c6e3fb2b062a | |
| parent | 04864f45b2f24e1268640cbde9203a7f769b6a79 [diff] [blame] |
[ARM]: add missing switch case for cortex-r52 Adds a missing switch case for handling cortex-r52 in init-subtarget-features. llvm-svn: 283551
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index a90b495..f39e792 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -244,6 +244,7 @@ case CortexR7: case CortexM3: case ExynosM1: + case CortexR52: break; case Krait: PreISelOperandLatencyAdjustment = 1;