whatever. Intermediate patch to see what breaks. Seems ok.
llvm-svn: 24260
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index ebbc444..fc9ace7 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -26,7 +26,9 @@
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == Alpha::BIS || oc == Alpha::CPYS) { // or r1, r2, r2 // cpys r1 r2 r2
+ if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) {
+ // or r1, r2, r2
+ // cpys(s|t) r1 r2 r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&