commit 9831d4058c0fb10fb3923905f073cd55fc2462d2
author Simon Pilgrim <llvm-dev@redking.me.uk> Sat Dec 15 12:25:22 2018 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Sat Dec 15 12:25:22 2018 +0000
tree 525cdd3e0bfd3b130d2e7424d6ad4d6604e0fa54
parent 1e1fd9c76119680e4c851baa77d7bf6a1762b8cb

Fix -Wunused-variable warning. NFCI.

llvm-svn: 349265

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 9f3983c..3d9de50 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -1112,6 +1112,7 @@
   BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
           TII->get(AMDGPU::S_MOV_B32), Reg)
     .addImm(Val);
+  (void)Mov;
   LLVM_DEBUG(dbgs() << "    "; Mov->dump());
   return MachineOperand::CreateReg(Reg, false);
 }
@@ -1146,6 +1147,7 @@
       .addReg(CarryReg, RegState::Define)
       .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg)
     .add(OffsetLo);
+  (void)LoHalf;
   LLVM_DEBUG(dbgs() << "    "; LoHalf->dump(););
 
   MachineInstr *HiHalf =
@@ -1154,6 +1156,7 @@
     .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg)
     .add(OffsetHi)
     .addReg(CarryReg, RegState::Kill);
+  (void)HiHalf;
   LLVM_DEBUG(dbgs() << "    "; HiHalf->dump(););
 
   unsigned FullDestReg = MRI->createVirtualRegister(&AMDGPU::VReg_64RegClass);
@@ -1163,6 +1166,7 @@
       .addImm(AMDGPU::sub0)
       .addReg(DestSub1)
       .addImm(AMDGPU::sub1);
+  (void)FullBase;
   LLVM_DEBUG(dbgs() << "    "; FullBase->dump(); dbgs() << "\n";);
 
   return FullDestReg;