Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
fields to use.
llvm-svn: 107952
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index b3e2e94..f0174b9 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -435,32 +435,27 @@
SSEDomainShift = 22,
OpcodeShift = 24,
- OpcodeMask = 0xFF << OpcodeShift
+ OpcodeMask = 0xFF << OpcodeShift,
- };
-
- // FIXME: The enum opcode space is over and more bits are needed. Anywhere
- // those enums below are used, TSFlags must be shifted right by 32 first.
- enum {
//===------------------------------------------------------------------===//
- // VEX - A prefix used by AVX instructions
- VEX = 1,
+ // VEX - The opcode prefix used by AVX instructions
+ VEX = 1ULL << 32,
- // VEX_W is has a opcode specific functionality, but is used in the same
+ // VEX_W - Has a opcode specific functionality, but is used in the same
// way as REX_W is for regular SSE instructions.
- VEX_W = 1 << 1,
+ VEX_W = 1ULL << 33,
- // VEX_4V is used to specify an additional AVX/SSE register. Several 2
+ // VEX_4V - Used to specify an additional AVX/SSE register. Several 2
// address instructions in SSE are represented as 3 address ones in AVX
// and the additional register is encoded in VEX_VVVV prefix.
- VEX_4V = 1 << 2,
+ VEX_4V = 1ULL << 34,
- // VEX_I8IMM specifies that the last register used in a AVX instruction,
+ // VEX_I8IMM - Specifies that the last register used in a AVX instruction,
// must be encoded in the i8 immediate field. This usually happens in
// instructions with 4 operands.
- VEX_I8IMM = 1 << 3
+ VEX_I8IMM = 1ULL << 35
};
-
+
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.
//
@@ -525,7 +520,7 @@
case X86II::MRMDestMem:
return 0;
case X86II::MRMSrcMem: {
- bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
+ bool HasVEX_4V = TSFlags & X86II::VEX_4V;
unsigned FirstMemOp = 1;
if (HasVEX_4V)
++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
diff --git a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
index 17bfa05..943284a 100644
--- a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
@@ -364,7 +364,7 @@
const TargetInstrDesc &Desc,
raw_ostream &OS) const {
bool HasVEX_4V = false;
- if ((TSFlags >> 32) & X86II::VEX_4V)
+ if (TSFlags & X86II::VEX_4V)
HasVEX_4V = true;
// VEX_R: opcode externsion equivalent to REX.R in
@@ -428,7 +428,7 @@
if (TSFlags & X86II::OpSize)
VEX_PP = 0x01;
- if ((TSFlags >> 32) & X86II::VEX_W)
+ if (TSFlags & X86II::VEX_W)
VEX_W = 1;
switch (TSFlags & X86II::Op0Mask) {
@@ -482,7 +482,7 @@
// If the last register should be encoded in the immediate field
// do not use any bit from VEX prefix to this register, ignore it
- if ((TSFlags >> 32) & X86II::VEX_I8IMM)
+ if (TSFlags & X86II::VEX_I8IMM)
NumOps--;
for (; CurOp != NumOps; ++CurOp) {
@@ -780,9 +780,9 @@
// It uses the VEX.VVVV field?
bool HasVEX_4V = false;
- if ((TSFlags >> 32) & X86II::VEX)
+ if (TSFlags & X86II::VEX)
HasVEXPrefix = true;
- if ((TSFlags >> 32) & X86II::VEX_4V)
+ if (TSFlags & X86II::VEX_4V)
HasVEX_4V = true;
// Determine where the memory operand starts, if present.
@@ -921,7 +921,7 @@
if (CurOp != NumOps) {
// The last source register of a 4 operand instruction in AVX is encoded
// in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
- if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
+ if (TSFlags & X86II::VEX_I8IMM) {
const MCOperand &MO = MI.getOperand(CurOp++);
bool IsExtReg =
X86InstrInfo::isX86_64ExtendedReg(MO.getReg());