commit 9a083a4121e026f917b0ccc8aaccdcc3543e14c8
author Evan Cheng <evan.cheng@apple.com> Tue Sep 12 21:04:05 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Tue Sep 12 21:04:05 2006 +0000
tree 28b6a09b7b1cbde3389768d65e0a6f7275822145
parent 45fe3bc72cbbfdca3ee2a8bf649982871b0bcba4

Reflects MachineConstantPoolEntry changes.

llvm-svn: 30279

llvm/lib/Target/Alpha/AlphaISelLowering.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
index fde5801..a9649ab 100644
--- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -436,7 +436,7 @@
   }
   case ISD::ConstantPool: {
     ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
-    Constant *C = CP->get();
+    Constant *C = CP->getConstVal();
     SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
     
     SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi,  MVT::i64, CPI,