commit 9b802e4650c5fe5ea0fc273a15536d1d6a67fbf9
author Ayman Musa <ayman.musa@intel.com> Wed Mar 01 10:20:48 2017 +0000
committer Ayman Musa <ayman.musa@intel.com> Wed Mar 01 10:20:48 2017 +0000
tree c8a3e49801b68ae196769beb06feb7ceddcfd91c
parent 9108644dbf54e4727728ab08c8b7e21bfcd12e8c

[X86] Fix creating vreg def after use. 

llvm-svn: 296601

llvm/lib/Target/X86/X86FastISel.cpp

diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 278d963..4a46cb0 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -2423,17 +2423,22 @@
   if (OpReg == 0)
     return false;
 
+  unsigned ImplicitDefReg;
+  if (Subtarget->hasAVX()) {
+    ImplicitDefReg = createResultReg(RC);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
+
+  }
+
   unsigned ResultReg = createResultReg(RC);
   MachineInstrBuilder MIB;
   MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),
                 ResultReg);
-  if (Subtarget->hasAVX()) {
-    unsigned ImplicitDefReg = createResultReg(RC);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-            TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
 
+  if (Subtarget->hasAVX())
     MIB.addReg(ImplicitDefReg);
-  }
+
   MIB.addReg(OpReg);
   updateValueMap(I, ResultReg);
   return true;