commit 9b9dea5d07bd024737327c36d23cb6f47d793bca
author Andrew Trick <atrick@apple.com> Wed Mar 07 23:00:59 2012 +0000
committer Andrew Trick <atrick@apple.com> Wed Mar 07 23:00:59 2012 +0000
tree 598e64030d0c3813695f3045ba880c13f7a932a3
parent 926d4736edde7a22059dfc040e31a35f6638d0d9

misched prep: Comment the ScheduleDAGInstrs interface.

llvm-svn: 152259

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index c4addee..d2351a3 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -38,8 +38,9 @@
                                      bool IsPostRAFlag,
                                      LiveIntervals *lis)
   : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
-    InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
-    LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
+    InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
+    IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
+    FirstDbgValue(0) {
   assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
   DbgValues.clear();
   assert(!(IsPostRA && MRI.getNumVirtRegs()) &&