commit 9c1d9fdeaa11e2f615c47235cc33bd199d3d08b2
author Craig Topper <craig.topper@intel.com> Thu Aug 16 06:20:24 2018 +0000
committer Craig Topper <craig.topper@intel.com> Thu Aug 16 06:20:24 2018 +0000
tree a320f4e2b0a1dfa9ac4bf2fe54d16a38a11104e0
parent 9d6983c9fde66fa12c0bc3898571ca2545e043cf

[X86] Remove masking from the 512-bit padds and psubs intrinsics. Use select in IR instead.

llvm-svn: 339842

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 7773c3d..1d0cd11 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -245,8 +245,7 @@
 
 static Value *simplifyX86AddsSubs(const IntrinsicInst &II,
                                   InstCombiner::BuilderTy &Builder) {
-  bool IsAddition = false;
-  bool IsMasked = false;
+  bool IsAddition;
 
   switch (II.getIntrinsicID()) {
   default: llvm_unreachable("Unexpected intrinsic!");
@@ -254,21 +253,17 @@
   case Intrinsic::x86_sse2_padds_w:
   case Intrinsic::x86_avx2_padds_b:
   case Intrinsic::x86_avx2_padds_w:
-    IsAddition = true; IsMasked = false;
+  case Intrinsic::x86_avx512_padds_b_512:
+  case Intrinsic::x86_avx512_padds_w_512:
+    IsAddition = true;
     break;
   case Intrinsic::x86_sse2_psubs_b:
   case Intrinsic::x86_sse2_psubs_w:
   case Intrinsic::x86_avx2_psubs_b:
   case Intrinsic::x86_avx2_psubs_w:
-    IsAddition = false; IsMasked = false;
-    break;
-  case Intrinsic::x86_avx512_mask_padds_b_512:
-  case Intrinsic::x86_avx512_mask_padds_w_512:
-    IsAddition = true; IsMasked = true;
-    break;
-  case Intrinsic::x86_avx512_mask_psubs_b_512:
-  case Intrinsic::x86_avx512_mask_psubs_w_512:
-    IsAddition = false; IsMasked = true;
+  case Intrinsic::x86_avx512_psubs_b_512:
+  case Intrinsic::x86_avx512_psubs_w_512:
+    IsAddition = false;
     break;
   }
 
@@ -278,7 +273,7 @@
   auto SVT = VT->getElementType();
   unsigned NumElems = VT->getNumElements();
 
-  if (!Arg0 || !Arg1 || (IsMasked && !isa<Constant>(II.getOperand(2))))
+  if (!Arg0 || !Arg1)
     return nullptr;
 
   SmallVector<Constant *, 64> Result;
@@ -306,21 +301,7 @@
     Result.push_back(Constant::getIntegerValue(SVT, ResultElem));
   }
 
-  Value *ResultVec = ConstantVector::get(Result);
-
-  if (II.getNumArgOperands() == 4) { // For masked intrinsics.
-    Value *Src = II.getOperand(2);
-    auto Mask = II.getOperand(3);
-    if (auto *C = dyn_cast<Constant>(Mask))
-      if (C->isAllOnesValue())
-        return ResultVec;
-    auto *MaskTy = VectorType::get(
-        Builder.getInt1Ty(), cast<IntegerType>(Mask->getType())->getBitWidth());
-    Mask = Builder.CreateBitCast(Mask, MaskTy);
-    ResultVec = Builder.CreateSelect(Mask, ResultVec, Src);
-  }
-
-  return ResultVec;
+  return ConstantVector::get(Result);
 }
 
 static Value *simplifyX86immShift(const IntrinsicInst &II,
@@ -2614,14 +2595,13 @@
   case Intrinsic::x86_avx2_padds_w:
   case Intrinsic::x86_avx2_psubs_b:
   case Intrinsic::x86_avx2_psubs_w:
-  case Intrinsic::x86_avx512_mask_padds_b_512:
-  case Intrinsic::x86_avx512_mask_padds_w_512:
-  case Intrinsic::x86_avx512_mask_psubs_b_512:
-  case Intrinsic::x86_avx512_mask_psubs_w_512:
+  case Intrinsic::x86_avx512_padds_b_512:
+  case Intrinsic::x86_avx512_padds_w_512:
+  case Intrinsic::x86_avx512_psubs_b_512:
+  case Intrinsic::x86_avx512_psubs_w_512:
     if (Value *V = simplifyX86AddsSubs(*II, Builder))
       return replaceInstUsesWith(*II, V);
     break;
-    
 
   // Constant fold ashr( <A x Bi>, Ci ).
   // Constant fold lshr( <A x Bi>, Ci ).