Add support for the 'l' constraint.
Patch by Jack Carter.
llvm-svn: 156294
diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
index aa186ec..94ded307 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
@@ -29,5 +29,16 @@
; CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
+; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
+; after the inline expression for a mflo to pull the value out of lo.
+; CHECK: #APP
+; CHECK-NEXT: mtlo ${{[0-9]+}}
+; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}}
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: mflo ${{[0-9]+}}
+ %bosco = alloca i32, align 4
+ call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
+ store volatile i32 %4, i32* %bosco, align 4
+
ret i32 0
}