argument lowering should copy from the vreg shadows of live-in arguments
passed in registers, not directly from the pregs themselves.
llvm-svn: 34838
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 65593eb..2fb89c3 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -627,8 +627,8 @@
RC = X86::VR128RegisterClass;
}
- SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
- AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+ unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+ SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted to 32
// bits. Insert an assert[sz]ext to capture this, then truncate to the
@@ -877,8 +877,8 @@
RC = X86::VR128RegisterClass;
}
- SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
- AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+ unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+ SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted to 32
// bits. Insert an assert[sz]ext to capture this, then truncate to the
@@ -1116,9 +1116,9 @@
assert(MVT::isVector(RegVT));
RC = X86::VR128RegisterClass;
}
-
- SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
- AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+
+ unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+ SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted to 32
// bits. Insert an assert[sz]ext to capture this, then truncate to the