commit 9cf980d4a7ac7bda6f05807dd1e0456b8b2906ff
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jul 30 23:56:30 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Jul 30 23:56:30 2019 +0000
tree 38497ac0b07bfbd3e5f811c6d2227f7ec3ce0a25
parent c1210c7e96fe8cabfa40b5cd155814d704fe9f3f

GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}

llvm-svn: 367369

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 7c90d57..3dc2200 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1984,7 +1984,6 @@
   unsigned Opcode = 0;
   switch (I.getOperation()) {
   default:
-    llvm_unreachable("Unknown atomicrmw op");
     return false;
   case AtomicRMWInst::Xchg:
     Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
@@ -2019,6 +2018,12 @@
   case AtomicRMWInst::UMin:
     Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
     break;
+  case AtomicRMWInst::FAdd:
+    Opcode = TargetOpcode::G_ATOMICRMW_FADD;
+    break;
+  case AtomicRMWInst::FSub:
+    Opcode = TargetOpcode::G_ATOMICRMW_FSUB;
+    break;
   }
 
   MIRBuilder.buildAtomicRMW(