commit 9d419d3b0cfda0f85d88633bd8620cd65ccb0498
author Francis Visoiu Mistrih <francisvm@yahoo.com> Tue Nov 28 12:42:37 2017 +0000
committer Francis Visoiu Mistrih <francisvm@yahoo.com> Tue Nov 28 12:42:37 2017 +0000
tree e1fa028a9c3a8d514e67b9bac321519331979dea
parent 8dc603b03147c91ff4e66b8bfc934aad6c4cb4b3

[CodeGen] Rename functions PrintReg* to printReg*

LLVM Coding Standards:
  Function names should be verb phrases (as they represent actions), and
  command-like function should be imperative. The name should be camel
  case, and start with a lower case letter (e.g. openFile() or isFoo()).

Differential Revision: https://reviews.llvm.org/D40416

llvm-svn: 319168

llvm/lib/Target/ARC/ARCInstrInfo.cpp

diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 48d5a00..a299e32 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -294,7 +294,7 @@
          "Only support 4-byte stores to stack now.");
   assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
          "Only support GPR32 stores to stack now.");
-  DEBUG(dbgs() << "Created store reg=" << PrintReg(SrcReg, TRI)
+  DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)
                << " to FrameIndex=" << FrameIndex << "\n");
   BuildMI(MBB, I, dl, get(ARC::ST_rs9))
       .addReg(SrcReg, getKillRegState(isKill))
@@ -321,7 +321,7 @@
          "Only support 4-byte loads from stack now.");
   assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
          "Only support GPR32 stores to stack now.");
-  DEBUG(dbgs() << "Created load reg=" << PrintReg(DestReg, TRI)
+  DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI)
                << " from FrameIndex=" << FrameIndex << "\n");
   BuildMI(MBB, I, dl, get(ARC::LD_rs9))
       .addReg(DestReg, RegState::Define)

llvm/lib/Target/ARC/ARCRegisterInfo.cpp

diff --git a/llvm/lib/Target/ARC/ARCRegisterInfo.cpp b/llvm/lib/Target/ARC/ARCRegisterInfo.cpp
index bed47a0..59b22c5 100644
--- a/llvm/lib/Target/ARC/ARCRegisterInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCRegisterInfo.cpp
@@ -66,8 +66,8 @@
           MBB.getParent()->getSubtarget().getRegisterInfo();
       BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
       assert(BaseReg && "Register scavenging failed.");
-      DEBUG(dbgs() << "Scavenged register " << PrintReg(BaseReg, TRI)
-                   << " for FrameReg=" << PrintReg(FrameReg, TRI)
+      DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
+                   << " for FrameReg=" << printReg(FrameReg, TRI)
                    << "+Offset=" << Offset << "\n");
       (void)TRI;
       RS->setRegUsed(BaseReg);