Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery
llvm-svn: 23735
diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp
index 8aaf76b..5c44230 100644
--- a/llvm/lib/Target/X86/X86ISelPattern.cpp
+++ b/llvm/lib/Target/X86/X86ISelPattern.cpp
@@ -184,8 +184,8 @@
if (X86ScalarSSE) {
// Set up the FP register classes.
- addRegisterClass(MVT::f32, X86::RXMMRegisterClass);
- addRegisterClass(MVT::f64, X86::RXMMRegisterClass);
+ addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
+ addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
// SSE has no load+extend ops
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
@@ -4192,10 +4192,10 @@
case MVT::i8: Opc = X86::MOV8rr; break;
case MVT::i16: Opc = X86::MOV16rr; break;
case MVT::i32: Opc = X86::MOV32rr; break;
- case MVT::f32: Opc = X86::MOVAPSrr; break;
+ case MVT::f32: Opc = X86::MOVSSrr; break;
case MVT::f64:
if (X86ScalarSSE) {
- Opc = X86::MOVAPDrr;
+ Opc = X86::MOVSDrr;
} else {
Opc = X86::FpMOV;
ContainsFPCode = true;