R600/SI: Start implementing an assembler
This was done using the Sparc and PowerPC AsmParsers as guides. So far it
is very simple and only supports sopp instructions.
llvm-svn: 221994
diff --git a/llvm/docs/R600Usage.rst b/llvm/docs/R600Usage.rst
new file mode 100644
index 0000000..48a30c8
--- /dev/null
+++ b/llvm/docs/R600Usage.rst
@@ -0,0 +1,43 @@
+============================
+User Guide for R600 Back-end
+============================
+
+Introduction
+============
+
+The R600 back-end provides ISA code generation for AMD GPUs, starting with
+the R600 family up until the current Sea Islands (GCN Gen 2).
+
+
+Assembler
+=========
+
+The assembler is currently a work in progress and not yet complete. Below
+are the currently supported features.
+
+SOPP Instructions
+-----------------
+
+Unless otherwise mentioned, all SOPP instructions that with an operand
+accept a integer operand(s) only. No verification is performed on the
+operands, so it is up to the programmer to be familiar with the range
+or acceptable values.
+
+s_waitcnt
+^^^^^^^^^
+
+s_waitcnt accepts named arguments to specify which memory counter(s) to
+wait for.
+
+.. code-block:: nasm
+
+ // Wait for all counters to be 0
+ s_waitcnt 0
+
+ // Equivalent to s_waitcnt 0. Counter names can also be delimited by
+ // '&' or ','.
+ s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
+
+ // Wait for vmcnt counter to be 1.
+ s_waitcnt vmcnt(1)
+
diff --git a/llvm/docs/index.rst b/llvm/docs/index.rst
index 403c17a..5ac5443 100644
--- a/llvm/docs/index.rst
+++ b/llvm/docs/index.rst
@@ -235,6 +235,7 @@
WritingAnLLVMPass
HowToUseAttributes
NVPTXUsage
+ R600Usage
StackMaps
InAlloca
BigEndianNEON
@@ -317,6 +318,9 @@
:doc:`NVPTXUsage`
This document describes using the NVPTX back-end to compile GPU kernels.
+:doc:`R600Usage`
+ This document describes how to use the R600 back-end.
+
:doc:`StackMaps`
LLVM support for mapping instruction addresses to the location of
values and allowing code to be patched.