[MC][Tablegen] Allow the definition of processor register files in the scheduling model for llvm-mca
This patch allows the description of register files in processor scheduling
models. This addresses PR36662.
A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td.
Targets can optionally describe register files for their processors using that
class. In particular, class RegisterFile allows to specify:
- The total number of physical registers.
- Which target registers are accessible through the register file.
- The cost of allocating a register at register renaming stage.
Example (from this patch - see file X86/X86ScheduleBtVer2.td)
def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>
Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar
(btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM
register definitions only cost 1 physical register.
The syntax allows to specify an empty set of register classes. An empty set of
register classes means: this register file models all the registers specified by
the Target. For each register class, users can specify an optional register
cost. By default, register costs default to 1. A value of 0 for the number of
physical registers means: "this register file has an unbounded number of
physical registers".
This patch is structured in two parts.
* Part 1 - MC/Tablegen *
A first part adds the tablegen definition of RegisterFile, and teaches the
SubtargetEmitter how to emit information related to register files.
Information about register files is accessible through an instance of
MCExtraProcessorInfo.
The idea behind this design is to logically partition the processor description
which is only used by external tools (like llvm-mca) from the processor
information used by the llvm machine schedulers.
I think that this design would make easier for targets to get rid of the extra
processor information if they don't want it.
* Part 2 - llvm-mca related *
The second part of this patch is related to changes to llvm-mca.
The main differences are:
1) class RegisterFile now needs to take into account the "cost of a register"
when allocating physical registers at register renaming stage.
2) Point 1. triggered a minor refactoring which lef to the removal of the
"maximum 32 register files" restriction.
3) The BackendStatistics view has been updated so that we can print out extra
details related to each register file implemented by the processor.
The effect of point 3. is also visible in tests register-files-[1..5].s.
Differential Revision: https://reviews.llvm.org/D44980
llvm-svn: 329067
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 7791f4a..5c52bdd 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -211,6 +211,9 @@
DEBUG(dbgs() << "\n+++ RESOURCE DEFINITIONS (collectProcResources) +++\n");
collectProcResources();
+ // Find register file definitions for each processor.
+ collectRegisterFiles();
+
checkCompleteness();
}
@@ -1486,6 +1489,30 @@
}
}
+// Collect all the RegisterFile definitions available in this target.
+void CodeGenSchedModels::collectRegisterFiles() {
+ RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile");
+
+ // RegisterFiles is the vector of CodeGenRegisterFile.
+ for (Record *RF : RegisterFileDefs) {
+ // For each register file definition, construct a CodeGenRegisterFile object
+ // and add it to the appropriate scheduling model.
+ CodeGenProcModel &PM = getProcModel(RF->getValueAsDef("SchedModel"));
+ PM.RegisterFiles.emplace_back(CodeGenRegisterFile(RF->getName(),RF));
+ CodeGenRegisterFile &CGRF = PM.RegisterFiles.back();
+
+ // Now set the number of physical registers as well as the cost of registers
+ // in each register class.
+ CGRF.NumPhysRegs = RF->getValueAsInt("NumPhysRegs");
+ RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");
+ std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
+ for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {
+ int Cost = RegisterCosts.size() > I ? RegisterCosts[I] : 1;
+ CGRF.Costs.emplace_back(RegisterClasses[I], Cost);
+ }
+ }
+}
+
// Collect and sort WriteRes, ReadAdvance, and ProcResources.
void CodeGenSchedModels::collectProcResources() {
ProcResourceDefs = Records.getAllDerivedDefinitions("ProcResourceUnits");
diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h
index 2d906bb..3882496 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/CodeGenSchedule.h
@@ -26,6 +26,7 @@
class CodeGenTarget;
class CodeGenSchedModels;
class CodeGenInstruction;
+class CodeGenRegisterClass;
using RecVec = std::vector<Record*>;
using RecIter = std::vector<Record*>::const_iterator;
@@ -157,6 +158,38 @@
#endif
};
+/// Represent the cost of allocating a register of register class RCDef.
+///
+/// The cost of allocating a register is equivalent to the number of physical
+/// registers used by the register renamer. Register costs are defined at
+/// register class granularity.
+struct CodeGenRegisterCost {
+ Record *RCDef;
+ unsigned Cost;
+ CodeGenRegisterCost(Record *RC, unsigned RegisterCost)
+ : RCDef(RC), Cost(RegisterCost) {}
+ CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
+ CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
+};
+
+/// A processor register file.
+///
+/// This class describes a processor register file. Register file information is
+/// currently consumed by external tools like llvm-mca to predict dispatch
+/// stalls due to register pressure.
+struct CodeGenRegisterFile {
+ std::string Name;
+ Record *RegisterFileDef;
+
+ unsigned NumPhysRegs;
+ std::vector<CodeGenRegisterCost> Costs;
+
+ CodeGenRegisterFile(StringRef name, Record *def)
+ : Name(name), RegisterFileDef(def), NumPhysRegs(0) {}
+
+ bool hasDefaultCosts() const { return Costs.empty(); }
+};
+
// Processor model.
//
// ModelName is a unique name used to name an instantiation of MCSchedModel.
@@ -199,6 +232,9 @@
// Per-operand machine model resources associated with this processor.
RecVec ProcResourceDefs;
+ // List of Register Files.
+ std::vector<CodeGenRegisterFile> RegisterFiles;
+
CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
Record *IDef) :
Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef) {}
@@ -211,6 +247,10 @@
return !WriteResDefs.empty() || !ItinRWDefs.empty();
}
+ bool hasExtraProcessorInfo() const {
+ return !RegisterFiles.empty();
+ }
+
unsigned getProcResourceIdx(Record *PRDef) const;
bool isUnsupported(const CodeGenInstruction &Inst) const;
@@ -396,6 +436,8 @@
void collectSchedClasses();
+ void collectRegisterFiles();
+
std::string createSchedClassName(Record *ItinClassDef,
ArrayRef<unsigned> OperWrites,
ArrayRef<unsigned> OperReads);
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 1501826..30d76f7 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -90,6 +90,7 @@
void EmitItineraries(raw_ostream &OS,
std::vector<std::vector<InstrItinerary>>
&ProcItinLists);
+ void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS);
void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
char Separator);
void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
@@ -604,6 +605,61 @@
OS << "};\n";
}
+void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
+ raw_ostream &OS) {
+ if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
+ return RF.hasDefaultCosts();
+ }))
+ return;
+
+ // Print the RegisterCost table first.
+ OS << "\n// {RegisterClassID, Register Cost}\n";
+ OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
+ << "RegisterCosts"
+ << "[] = {\n";
+
+ for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
+ // Skip register files with a default cost table.
+ if (RF.hasDefaultCosts())
+ continue;
+ // Add entries to the cost table.
+ for (const CodeGenRegisterCost &RC : RF.Costs) {
+ OS << " { ";
+ Record *Rec = RC.RCDef;
+ if (Rec->getValue("Namespace"))
+ OS << Rec->getValueAsString("Namespace") << "::";
+ OS << Rec->getName() << "RegClassID, " << RC.Cost << "},\n";
+ }
+ }
+ OS << "};\n";
+
+ // Now generate a table with register file info.
+ OS << "\n // {Name, #PhysRegs, #CostEntries, IndexToCostTbl}\n";
+ OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
+ << "RegisterFiles"
+ << "[] = {\n"
+ << " { \"InvalidRegisterFile\", 0, 0, 0 },\n";
+ unsigned CostTblIndex = 0;
+
+ for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
+ OS << " { ";
+ OS << '"' << RD.Name << '"' << ", " << RD.NumPhysRegs << ", ";
+ unsigned NumCostEntries = RD.Costs.size();
+ OS << NumCostEntries << ", " << CostTblIndex << "},\n";
+ CostTblIndex += NumCostEntries;
+ }
+ OS << "};\n";
+
+ // Now generate a table for the extra processor info.
+ OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
+ << "ExtraInfo = {\n " << ProcModel.ModelName << "RegisterFiles,\n "
+ << (1 + ProcModel.RegisterFiles.size())
+ << ", // Number of register files.\n "
+ << ProcModel.ModelName << "RegisterCosts,\n " << CostTblIndex
+ << " // Number of register cost entries.\n"
+ << "};\n";
+}
+
void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
raw_ostream &OS) {
EmitProcessorResourceSubUnits(ProcModel, OS);
@@ -1157,6 +1213,9 @@
void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
// For each processor model.
for (const CodeGenProcModel &PM : SchedModels.procModels()) {
+ // Emit extra processor info if available.
+ if (PM.hasExtraProcessorInfo())
+ EmitExtraProcessorInfo(PM, OS);
// Emit processor resource table.
if (PM.hasInstrSchedModel())
EmitProcessorResources(PM, OS);
@@ -1197,9 +1256,13 @@
OS << " nullptr, nullptr, 0, 0,"
<< " // No instruction-level machine model.\n";
if (PM.hasItineraries())
- OS << " " << PM.ItinsDef->getName() << "\n";
+ OS << " " << PM.ItinsDef->getName() << ",\n";
else
- OS << " nullptr // No Itinerary\n";
+ OS << " nullptr, // No Itinerary\n";
+ if (PM.hasExtraProcessorInfo())
+ OS << " &" << PM.ModelName << "ExtraInfo\n";
+ else
+ OS << " nullptr // No extra processor descriptor\n";
OS << "};\n";
}
}