commit 9dba67f431610e4ab56e3f1acdbb2c41a114be93
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Feb 11 17:05:20 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Feb 11 17:05:20 2019 +0000
tree 76cf17e15ff6d199cfa46d2afa5cc58fc3a70bf0
parent 9bbb721eb275002816e77fd267e23270508b2cd2

GlobalISel: Add G_FCANONICALIZE instruction

llvm-svn: 353719

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index ab9d980..19bff7f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -806,6 +806,8 @@
       return TargetOpcode::G_FEXP2;
     case Intrinsic::fabs:
       return TargetOpcode::G_FABS;
+    case Intrinsic::canonicalize:
+      return TargetOpcode::G_FCANONICALIZE;
     case Intrinsic::log:
       return TargetOpcode::G_FLOG;
     case Intrinsic::log2:

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 367afc6..9dcdb0d 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -1354,6 +1354,7 @@
   case TargetOpcode::G_FMA:
   case TargetOpcode::G_FNEG:
   case TargetOpcode::G_FABS:
+  case TargetOpcode::G_FCANONICALIZE:
   case TargetOpcode::G_FDIV:
   case TargetOpcode::G_FREM:
   case TargetOpcode::G_FCEIL:
@@ -2135,6 +2136,7 @@
   case G_FSUB:
   case G_FNEG:
   case G_FABS:
+  case G_FCANONICALIZE:
   case G_FDIV:
   case G_FREM:
   case G_FMA: