Revert 51b0da73 "Recommit "[X86] Merge the FEATURE_64BIT and FEATURE_EM64T bits in X86TargetParser.def.""
It gets miscompiled with GCC 5.3, causing Clang to crash with
"error: unknown target CPU 'x86-64'"
See the llvm-commits thread for reproduction steps.
This reverts commit 51b0da731af75c68dd521e04cc576d5a611b1612.
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp
index 7e87d65..261e296 100644
--- a/llvm/lib/Support/X86TargetParser.cpp
+++ b/llvm/lib/Support/X86TargetParser.cpp
@@ -48,14 +48,6 @@
return (Bits[I / 32] & Mask) != 0;
}
- constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
- for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
- uint32_t NewBits = Bits[I] & RHS.Bits[I];
- Bits[I] = NewBits;
- }
- return *this;
- }
-
constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
uint32_t NewBits = Bits[I] | RHS.Bits[I];
@@ -65,14 +57,16 @@
}
constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
- FeatureBitset Result = *this;
- Result &= RHS;
+ FeatureBitset Result;
+ for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
+ Result.Bits[I] = Bits[I] & RHS.Bits[I];
return Result;
}
constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
- FeatureBitset Result = *this;
- Result |= RHS;
+ FeatureBitset Result;
+ for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
+ Result.Bits[I] = Bits[I] | RHS.Bits[I];
return Result;
}
@@ -117,10 +111,10 @@
static constexpr FeatureBitset FeaturesPrescott =
FeaturesPentium4 | FeatureSSE3;
static constexpr FeatureBitset FeaturesNocona =
- FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
+ FeaturesPrescott | FeatureEM64T | FeatureCMPXCHG16B;
// Basic 64-bit capable CPU.
-static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
+static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | FeatureEM64T;
// Intel Core CPUs
static constexpr FeatureBitset FeaturesCore2 =
@@ -207,7 +201,7 @@
static constexpr FeatureBitset FeaturesAthlonXP =
FeaturesAthlon | FeatureFXSR | FeatureSSE;
static constexpr FeatureBitset FeaturesK8 =
- FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
+ FeaturesAthlonXP | FeatureSSE2 | FeatureEM64T;
static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
static constexpr FeatureBitset FeaturesAMDFAM10 =
FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
@@ -215,7 +209,7 @@
// Bobcat architecture processors.
static constexpr FeatureBitset FeaturesBTVER1 =
- FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
+ FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T |
FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
FeatureSAHF;
@@ -226,7 +220,7 @@
// AMD Bulldozer architecture processors.
static constexpr FeatureBitset FeaturesBDVER1 =
FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
- FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
+ FeatureCMPXCHG16B | FeatureEM64T | FeatureFMA4 | FeatureFXSR | FeatureLWP |
FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
@@ -242,7 +236,7 @@
static constexpr FeatureBitset FeaturesZNVER1 =
FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
- FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
+ FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureEM64T | FeatureF16C |
FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
@@ -369,7 +363,7 @@
X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
for (const auto &P : Processors)
- if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
+ if (P.Name == CPU && (P.Features[FEATURE_EM64T] || !Only64Bit))
return P.Kind;
return CK_None;
@@ -378,7 +372,7 @@
void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
bool Only64Bit) {
for (const auto &P : Processors)
- if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
+ if (!P.Name.empty() && (P.Features[FEATURE_EM64T] || !Only64Bit))
Values.emplace_back(P.Name);
}
@@ -407,6 +401,7 @@
static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
+static constexpr FeatureBitset ImpliedFeaturesEM64T = {};
static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
@@ -532,14 +527,8 @@
[&](const ProcInfo &P) { return P.Name == CPU; });
assert(I != std::end(Processors) && "Processor not found!");
- FeatureBitset Bits = I->Features;
-
- // Remove the 64-bit feature which we only use to validate if a CPU can
- // be used with 64-bit mode.
- Bits &= ~Feature64BIT;
-
// Add the string version of all set bits.
- getFeatureBitsAsStrings(Bits, EnabledFeatures);
+ getFeatureBitsAsStrings(I->Features, EnabledFeatures);
}
// For each feature that is (transitively) implied by this feature, set it.