commit 9f75a55329d5157c67fe9f800ca5a7472634e44b
author Chris Lattner <sabre@nondot.org> Sat Feb 14 06:00:36 2004 +0000
committer Chris Lattner <sabre@nondot.org> Sat Feb 14 06:00:36 2004 +0000
tree 8a85721dd2215bc6d9a1a4b2b723c7aa50139f25
parent 0c48a03374cd7bc566e3e5f1df2d83879e019d03

finegrainify namespacification, fix 80col prob

llvm-svn: 11445

llvm/lib/Target/X86/InstSelectSimple.cpp

diff --git a/llvm/lib/Target/X86/InstSelectSimple.cpp b/llvm/lib/Target/X86/InstSelectSimple.cpp
index d4a5ac2..6129c74 100644
--- a/llvm/lib/Target/X86/InstSelectSimple.cpp
+++ b/llvm/lib/Target/X86/InstSelectSimple.cpp
@@ -1257,7 +1257,7 @@
       switch (Align & 3) {
       case 2:   // WORD aligned
         if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
-          CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
+          CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
         } else {
           CountReg = makeAnotherReg(Type::IntTy);
           BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(1);
@@ -1267,7 +1267,7 @@
         break;
       case 0:   // DWORD aligned
         if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
-          CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
+          CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
         } else {
           CountReg = makeAnotherReg(Type::IntTy);
           BuildMI(BB, X86::SHRir32, 2, CountReg).addReg(ByteReg).addZImm(2);