[X86] Give ADC8/16/32/64mi the same scheduling information as ADC8/16/32/64mr and SBB8/16/32/64mi.
It doesn't make a lot of sense that it would be different.
llvm-svn: 328946
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index de54837..7e9f3c4 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -2076,19 +2076,13 @@
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
-def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
- let Latency = 8;
- let NumMicroOps = 6;
- let ResourceCycles = [1,1,1,3];
-}
-def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;
-
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
-def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr",
+def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mi",
+ "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"SBB(8|16|32|64)mi",
"SBB(8|16|32|64)mr")>;