AMDGPU/GlobalISel: Fix scc->vcc copy handling
This was checking the size of the register with the value of the size,
which happens to be exec. Also fix assuming VCC is 64-bit to fix
wave32.
Also remove some untested handling for physical registers which is
skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical
copy source. I'm not sure if this should be trying to handle this
special case instead of dealing with this in copyPhysReg.
llvm-svn: 364761
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index c7237e4..ce45eab 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -60,11 +60,7 @@
const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
static bool isSCC(unsigned Reg, const MachineRegisterInfo &MRI) {
- if (Reg == AMDGPU::SCC)
- return true;
-
- if (TargetRegisterInfo::isPhysicalRegister(Reg))
- return false;
+ assert(!TargetRegisterInfo::isPhysicalRegister(Reg));
auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
const TargetRegisterClass *RC =
@@ -77,6 +73,22 @@
return RB->getID() == AMDGPU::SCCRegBankID;
}
+static bool isVCC(unsigned Reg, const MachineRegisterInfo &MRI,
+ const SIRegisterInfo &TRI) {
+ assert(!TargetRegisterInfo::isPhysicalRegister(Reg));
+
+ auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
+ const TargetRegisterClass *RC =
+ RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
+ if (RC) {
+ return RC == TRI.getWaveMaskRegClass() &&
+ MRI.getType(Reg).getSizeInBits() == 1;
+ }
+
+ const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
+ return RB->getID() == AMDGPU::VCCRegBankID;
+}
+
bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
@@ -88,14 +100,12 @@
const MachineOperand &Src = I.getOperand(1);
unsigned SrcReg = Src.getReg();
if (!TargetRegisterInfo::isPhysicalRegister(SrcReg) && isSCC(SrcReg, MRI)) {
- unsigned DstReg = TRI.getRegSizeInBits(I.getOperand(0).getReg(), MRI);
- unsigned DstSize = TRI.getRegSizeInBits(DstReg, MRI);
+ unsigned DstReg = I.getOperand(0).getReg();
- // We have a copy from a 32-bit to 64-bit register. This happens
- // when we are selecting scc->vcc copies.
- if (DstSize == 64) {
+ // Specially handle scc->vcc copies.
+ if (isVCC(DstReg, MRI, TRI)) {
const DebugLoc &DL = I.getDebugLoc();
- BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), I.getOperand(0).getReg())
+ BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
.addImm(0)
.addReg(SrcReg);
if (!MRI.getRegClassOrNull(SrcReg))
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 3579c2f..8181afc 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1690,8 +1690,8 @@
case AMDGPU::VGPRRegBankID:
return &AMDGPU::VGPR_32RegClass;
case AMDGPU::VCCRegBankID:
- // TODO: Check wavesize
- return &AMDGPU::SReg_64_XEXECRegClass;
+ return isWave32 ?
+ &AMDGPU::SReg_32_XM0_XEXECRegClass : &AMDGPU::SReg_64_XEXECRegClass;
case AMDGPU::SGPRRegBankID:
return &AMDGPU::SReg_32_XM0RegClass;
case AMDGPU::SCCRegBankID: