commit a0be5a06c1d06df8bc0e4871eed7d31cf4e6869a
author Craig Topper <craig.topper@intel.com> Sun Dec 10 19:47:56 2017 +0000
committer Craig Topper <craig.topper@intel.com> Sun Dec 10 19:47:56 2017 +0000
tree e3aecd340f78fa866c2d31c3ff1a8c8695258054
parent 58946cdb087561fa75065f3557b00919bc891ac4

[X86] Rename some instructions that start with Int_ to have the _Int at the end.

This matches AVX512 version and is more consistent overall. And improves our scheduler models.

In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.

llvm-svn: 320325

llvm/lib/Target/X86/X86SchedHaswell.td

diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 24dd081..c8a876a 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -3122,7 +3122,7 @@
 def: InstRW<[HWWriteResGroup73], (instregex "CVTPD2DQrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "CVTPD2PSrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "CVTSD2SSrr")>;
-def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SD64rr")>;
+def: InstRW<[HWWriteResGroup73], (instregex "CVTSI642SDrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SDrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SSrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "CVTTPD2DQrr")>;
@@ -3136,7 +3136,7 @@
 def: InstRW<[HWWriteResGroup73], (instregex "VCVTPD2PSrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "VCVTPS2PHrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSD2SSrr")>;
-def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SD64rr")>;
+def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI642SDrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SDrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SSrr")>;
 def: InstRW<[HWWriteResGroup73], (instregex "VCVTTPD2DQrr")>;
@@ -3688,12 +3688,12 @@
   let NumMicroOps = 3;
   let ResourceCycles = [1,2];
 }
-def: InstRW<[HWWriteResGroup93], (instregex "CVTSI2SS64rr")>;
+def: InstRW<[HWWriteResGroup93], (instregex "CVTSI642SSrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "HADDPDrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "HADDPSrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "HSUBPDrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "HSUBPSrr")>;
-def: InstRW<[HWWriteResGroup93], (instregex "VCVTSI2SS64rr")>;
+def: InstRW<[HWWriteResGroup93], (instregex "VCVTSI642SSrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "VHADDPDYrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "VHADDPDrr")>;
 def: InstRW<[HWWriteResGroup93], (instregex "VHADDPSYrr")>;