[X86] Rename some instructions that start with Int_ to have the _Int at the end.
This matches AVX512 version and is more consistent overall. And improves our scheduler models.
In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses.
llvm-svn: 320325
diff --git a/llvm/test/CodeGen/X86/avx512-schedule.ll b/llvm/test/CodeGen/X86/avx512-schedule.ll
index d79daf8..85b0553 100755
--- a/llvm/test/CodeGen/X86/avx512-schedule.ll
+++ b/llvm/test/CodeGen/X86/avx512-schedule.ll
@@ -1849,12 +1849,12 @@
define <4 x float> @f64tof32_inreg(<2 x double> %a0, <4 x float> %a1) nounwind {
; GENERIC-LABEL: f64tof32_inreg:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vcvtsd2ss %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vcvtsd2ss %xmm0, %xmm1, %xmm0 # sched: [4:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f64tof32_inreg:
; SKX: # %bb.0:
-; SKX-NEXT: vcvtsd2ss %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
+; SKX-NEXT: vcvtsd2ss %xmm0, %xmm1, %xmm0 # sched: [5:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%ext = extractelement <2 x double> %a0, i32 0
%cvt = fptrunc double %ext to float
@@ -1897,12 +1897,12 @@
define <2 x double> @f32tof64_inreg(<2 x double> %a0, <4 x float> %a1) nounwind {
; GENERIC-LABEL: f32tof64_inreg:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; GENERIC-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: f32tof64_inreg:
; SKX: # %bb.0:
-; SKX-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
+; SKX-NEXT: vcvtss2sd %xmm1, %xmm0, %xmm0 # sched: [5:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%ext = extractelement <4 x float> %a1, i32 0
%cvt = fpext float %ext to double
diff --git a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
index 6f9737d..dd7dd27 100755
--- a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
+++ b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir
@@ -2124,97 +2124,97 @@
%xmm0 = VSQRTSSZr %xmm0, %noreg
; CHECK: %xmm0 = VSQRTSSr_Int %xmm0, %noreg
%xmm0 = VSQRTSSZr_Int %xmm0, %noreg
- ; CHECK: %rdi = VCVTSD2SI64rr %xmm0
- %rdi = VCVTSD2SI64Zrr %xmm0
- ; CHECK: %edi = VCVTSD2SIrr %xmm0
- %edi = VCVTSD2SIZrr %xmm0
+ ; CHECK: %rdi = VCVTSD2SI64rr_Int %xmm0
+ %rdi = VCVTSD2SI64Zrr_Int %xmm0
+ ; CHECK: %edi = VCVTSD2SIrr_Int %xmm0
+ %edi = VCVTSD2SIZrr_Int %xmm0
; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSD2SSZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSD2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSD2SSrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSD2SSZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSD2SSrr %xmm0, %noreg
%xmm0 = VCVTSD2SSZrr %xmm0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSD2SSrr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSD2SSrr_Int %xmm0, %noreg
%xmm0 = VCVTSD2SSZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSI2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SDZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSI2SDrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SDZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSI2SDrr %xmm0, %noreg
%xmm0 = VCVTSI2SDZrr %xmm0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SDrr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSI2SDrr_Int %xmm0, %noreg
%xmm0 = VCVTSI2SDZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSI2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SSZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSI2SSrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SSZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSI2SSrr %xmm0, %noreg
%xmm0 = VCVTSI2SSZrr %xmm0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SSrr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSI2SSrr_Int %xmm0, %noreg
%xmm0 = VCVTSI2SSZrr_Int %xmm0, %noreg
- ; CHECK: %xmm0 = VCVTSI2SD64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SDZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SD64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SDrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SDZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = VCVTSI2SD64rr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SDrr %xmm0, %noreg
%xmm0 = VCVTSI642SDZrr %xmm0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SD64rr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SDrr_Int %xmm0, %noreg
%xmm0 = VCVTSI642SDZrr_Int %xmm0, %noreg
- ; CHECK: %xmm0 = VCVTSI2SS64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SSZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SS64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SSrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SSZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = VCVTSI2SS64rr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SSrr %xmm0, %noreg
%xmm0 = VCVTSI642SSZrr %xmm0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSI2SS64rr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSI642SSrr_Int %xmm0, %noreg
%xmm0 = VCVTSI642SSZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSS2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
+ ; CHECK: %xmm0 = VCVTSS2SDrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSS2SDZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, %noreg
%xmm0 = VCVTSS2SDZrr %xmm0, %noreg
- ; CHECK: %xmm0 = Int_VCVTSS2SDrr %xmm0, %noreg
+ ; CHECK: %xmm0 = VCVTSS2SDrr_Int %xmm0, %noreg
%xmm0 = VCVTSS2SDZrr_Int %xmm0, %noreg
- ; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, %noreg, 0
- %rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, %noreg, 0
- ; CHECK: %rdi = VCVTSS2SI64rr %xmm0
- %rdi = VCVTSS2SI64Zrr %xmm0
- ; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, %noreg, 0
- %edi = VCVTSS2SIZrm %rdi, %xmm0, 1, %noreg, 0
- ; CHECK: %edi = VCVTSS2SIrr %xmm0
- %edi = VCVTSS2SIZrr %xmm0
+ ; CHECK: %rdi = VCVTSS2SI64rm_Int %rdi, %xmm0, 1, %noreg, 0
+ %rdi = VCVTSS2SI64Zrm_Int %rdi, %xmm0, 1, %noreg, 0
+ ; CHECK: %rdi = VCVTSS2SI64rr_Int %xmm0
+ %rdi = VCVTSS2SI64Zrr_Int %xmm0
+ ; CHECK: %edi = VCVTSS2SIrm_Int %rdi, %xmm0, 1, %noreg, 0
+ %edi = VCVTSS2SIZrm_Int %rdi, %xmm0, 1, %noreg, 0
+ ; CHECK: %edi = VCVTSS2SIrr_Int %xmm0
+ %edi = VCVTSS2SIZrr_Int %xmm0
; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm %rdi, %xmm0, 1, %noreg, 0
- ; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, %noreg, 0
+ ; CHECK: %rdi = VCVTTSD2SI64rm_Int %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = VCVTTSD2SI64rr %xmm0
%rdi = VCVTTSD2SI64Zrr %xmm0
- ; CHECK: %rdi = Int_VCVTTSD2SI64rr %xmm0
+ ; CHECK: %rdi = VCVTTSD2SI64rr_Int %xmm0
%rdi = VCVTTSD2SI64Zrr_Int %xmm0
; CHECK: %edi = VCVTTSD2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSD2SIZrm %rdi, %xmm0, 1, %noreg, 0
- ; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, %noreg, 0
+ ; CHECK: %edi = VCVTTSD2SIrm_Int %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSD2SIZrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = VCVTTSD2SIrr %xmm0
%edi = VCVTTSD2SIZrr %xmm0
- ; CHECK: %edi = Int_VCVTTSD2SIrr %xmm0
+ ; CHECK: %edi = VCVTTSD2SIrr_Int %xmm0
%edi = VCVTTSD2SIZrr_Int %xmm0
; CHECK: %rdi = VCVTTSS2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSS2SI64Zrm %rdi, %xmm0, 1, %noreg, 0
- ; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, %noreg, 0
+ ; CHECK: %rdi = VCVTTSS2SI64rm_Int %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = VCVTTSS2SI64rr %xmm0
%rdi = VCVTTSS2SI64Zrr %xmm0
- ; CHECK: %rdi = Int_VCVTTSS2SI64rr %xmm0
+ ; CHECK: %rdi = VCVTTSS2SI64rr_Int %xmm0
%rdi = VCVTTSS2SI64Zrr_Int %xmm0
; CHECK: %edi = VCVTTSS2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSS2SIZrm %rdi, %xmm0, 1, %noreg, 0
- ; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, %noreg, 0
+ ; CHECK: %edi = VCVTTSS2SIrm_Int %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSS2SIZrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = VCVTTSS2SIrr %xmm0
%edi = VCVTTSS2SIZrr %xmm0
- ; CHECK: %edi = Int_VCVTTSS2SIrr %xmm0
+ ; CHECK: %edi = VCVTTSS2SIrr_Int %xmm0
%edi = VCVTTSS2SIZrr_Int %xmm0
; CHECK: %xmm0 = VMOV64toSDrr %rdi
%xmm0 = VMOV64toSDZrr %rdi
@@ -4440,14 +4440,14 @@
%xmm16 = VSQRTSSZr %xmm16, %noreg
; CHECK: %xmm16 = VSQRTSSZr_Int %xmm16, %noreg
%xmm16 = VSQRTSSZr_Int %xmm16, %noreg
- ; CHECK: %rdi = VCVTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
- %rdi = VCVTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
- ; CHECK: %rdi = VCVTSD2SI64Zrr %xmm16
- %rdi = VCVTSD2SI64Zrr %xmm16
- ; CHECK: %edi = VCVTSD2SIZrm %rdi, %xmm16, 1, %noreg, 0
- %edi = VCVTSD2SIZrm %rdi, %xmm16, 1, %noreg, 0
- ; CHECK: %edi = VCVTSD2SIZrr %xmm16
- %edi = VCVTSD2SIZrr %xmm16
+ ; CHECK: %rdi = VCVTSD2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
+ %rdi = VCVTSD2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
+ ; CHECK: %rdi = VCVTSD2SI64Zrr_Int %xmm16
+ %rdi = VCVTSD2SI64Zrr_Int %xmm16
+ ; CHECK: %edi = VCVTSD2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
+ %edi = VCVTSD2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
+ ; CHECK: %edi = VCVTSD2SIZrr_Int %xmm16
+ %edi = VCVTSD2SIZrr_Int %xmm16
; CHECK: %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
@@ -4496,14 +4496,14 @@
%xmm16 = VCVTSS2SDZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSS2SDZrr_Int %xmm16, %noreg
%xmm16 = VCVTSS2SDZrr_Int %xmm16, %noreg
- ; CHECK: %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
- %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
- ; CHECK: %rdi = VCVTSS2SI64Zrr %xmm16
- %rdi = VCVTSS2SI64Zrr %xmm16
- ; CHECK: %edi = VCVTSS2SIZrm %rdi, %xmm16, 1, %noreg, 0
- %edi = VCVTSS2SIZrm %rdi, %xmm16, 1, %noreg, 0
- ; CHECK: %edi = VCVTSS2SIZrr %xmm16
- %edi = VCVTSS2SIZrr %xmm16
+ ; CHECK: %rdi = VCVTSS2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
+ %rdi = VCVTSS2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
+ ; CHECK: %rdi = VCVTSS2SI64Zrr_Int %xmm16
+ %rdi = VCVTSS2SI64Zrr_Int %xmm16
+ ; CHECK: %edi = VCVTSS2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
+ %edi = VCVTSS2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
+ ; CHECK: %edi = VCVTSS2SIZrr_Int %xmm16
+ %edi = VCVTSS2SIZrr_Int %xmm16
; CHECK: %rdi = VCVTTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
diff --git a/llvm/test/CodeGen/X86/sse-schedule.ll b/llvm/test/CodeGen/X86/sse-schedule.ll
index 6072e92..1b13a84 100644
--- a/llvm/test/CodeGen/X86/sse-schedule.ll
+++ b/llvm/test/CodeGen/X86/sse-schedule.ll
@@ -377,7 +377,7 @@
; GENERIC-LABEL: test_cmpss:
; GENERIC: # %bb.0:
; GENERIC-NEXT: cmpeqss %xmm1, %xmm0 # sched: [3:1.00]
-; GENERIC-NEXT: cmpeqss (%rdi), %xmm0 # sched: [7:1.00]
+; GENERIC-NEXT: cmpeqss (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_cmpss:
@@ -395,7 +395,7 @@
; SANDY-LABEL: test_cmpss:
; SANDY: # %bb.0:
; SANDY-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SANDY-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SANDY-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_cmpss:
@@ -412,14 +412,14 @@
;
; SKYLAKE-LABEL: test_cmpss:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmpss:
; SKX: # %bb.0:
-; SKX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKX-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; SKX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKX-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_cmpss:
diff --git a/llvm/test/CodeGen/X86/sse2-schedule.ll b/llvm/test/CodeGen/X86/sse2-schedule.ll
index 32c44c6..ad2edfe 100644
--- a/llvm/test/CodeGen/X86/sse2-schedule.ll
+++ b/llvm/test/CodeGen/X86/sse2-schedule.ll
@@ -452,7 +452,7 @@
; GENERIC-LABEL: test_cmpsd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: cmpeqsd %xmm1, %xmm0 # sched: [3:1.00]
-; GENERIC-NEXT: cmpeqsd (%rdi), %xmm0 # sched: [7:1.00]
+; GENERIC-NEXT: cmpeqsd (%rdi), %xmm0 # sched: [9:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; ATOM-LABEL: test_cmpsd:
@@ -470,7 +470,7 @@
; SANDY-LABEL: test_cmpsd:
; SANDY: # %bb.0:
; SANDY-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SANDY-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
+; SANDY-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [9:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_cmpsd:
@@ -487,14 +487,14 @@
;
; SKYLAKE-LABEL: test_cmpsd:
; SKYLAKE: # %bb.0:
-; SKYLAKE-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKYLAKE-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; SKYLAKE-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKYLAKE-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKYLAKE-NEXT: retq # sched: [7:1.00]
;
; SKX-LABEL: test_cmpsd:
; SKX: # %bb.0:
-; SKX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
-; SKX-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; SKX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
+; SKX-NEXT: vcmpeqsd (%rdi), %xmm0, %xmm0 # sched: [9:0.50]
; SKX-NEXT: retq # sched: [7:1.00]
;
; BTVER2-LABEL: test_cmpsd: