[TableGen] Support combining AssemblerPredicates with ORs
For context, the proposed RISC-V bit manipulation extension has a subset
of instructions which require one of two SubtargetFeatures to be
enabled, 'zbb' or 'zbp', and there is no defined feature which both of
these can imply to use as a constraint either (see comments in D65649).
AssemblerPredicates allow multiple SubtargetFeatures to be declared in
the "AssemblerCondString" field, separated by commas, and this means
that the two features must both be enabled. There is no equivalent to
say that _either_ feature X or feature Y must be enabled, short of
creating a dummy SubtargetFeature for this purpose and having features X
and Y imply the new feature.
To solve the case where X or Y is needed without adding a new feature,
and to better match a typical TableGen style, this replaces the existing
"AssemblerCondString" with a dag "AssemblerCondDag" which represents the
same information. Two operators are defined for use with
AssemblerCondDag, "all_of", which matches the current behaviour, and
"any_of", which adds the new proposed ORing features functionality.
This was originally proposed in the RFC at
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html
Changes to all current backends are mechanical to support the replaced
functionality, and are NFCI.
At this stage, it is illegal to combine features with ands and ors in a
single AssemblerCondDag. I suspect this case is sufficiently rare that
adding more complex changes to support it are unnecessary.
Differential Revision: https://reviews.llvm.org/D74338
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index f2700b4..b8913c3 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -941,21 +941,35 @@
for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) {
Record *R = *I;
- StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
+ const DagInit *D = R->getValueAsDag("AssemblerCondDag");
+ std::string CombineType = D->getOperator()->getAsString();
+ if (CombineType != "any_of" && CombineType != "all_of")
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ if (D->getNumArgs() == 0)
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ bool IsOr = CombineType == "any_of";
- // AsmCondString has syntax [!]F(,[!]F)*
- SmallVector<StringRef, 4> Ops;
- SplitString(AsmCondString, Ops, ",");
- assert(!Ops.empty() && "AssemblerCondString cannot be empty");
+ for (auto *Arg : D->getArgs()) {
+ bool IsNeg = false;
+ if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
+ if (NotArg->getOperator()->getAsString() != "not" ||
+ NotArg->getNumArgs() != 1)
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ Arg = NotArg->getArg(0);
+ IsNeg = true;
+ }
+ if (!isa<DefInit>(Arg) ||
+ !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
- for (StringRef Op : Ops) {
- assert(!Op.empty() && "Empty operator");
- bool IsNeg = Op[0] == '!';
- StringRef Feature = Op.drop_front(IsNeg ? 1 : 0);
- IAP.addCond(
- std::string(formatv("AliasPatternCond::K_{0}Feature, {1}::{2}",
- IsNeg ? "Neg" : "", Namespace, Feature)));
+ IAP.addCond(std::string(formatv(
+ "AliasPatternCond::K_{0}{1}Feature, {2}::{3}", IsOr ? "Or" : "",
+ IsNeg ? "Neg" : "", Namespace, Arg->getAsString())));
}
+ // If an AssemblerPredicate with ors is used, note end of list should
+ // these be combined.
+ if (IsOr)
+ IAP.addCond("AliasPatternCond::K_EndOrFeatures, 0");
}
IAPrinterMap[Aliases.first].push_back(std::move(IAP));
diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
index b587029..88d210f 100644
--- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -1182,15 +1182,6 @@
return (unsigned)(P - Decoders.begin());
}
-static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
- const std::string &PredicateNamespace) {
- if (str[0] == '!')
- o << "!Bits[" << PredicateNamespace << "::"
- << str.slice(1,str.size()) << "]";
- else
- o << "Bits[" << PredicateNamespace << "::" << str << "]";
-}
-
bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
unsigned Opc) const {
ListInit *Predicates =
@@ -1201,21 +1192,50 @@
if (!Pred->getValue("AssemblerMatcherPredicate"))
continue;
- StringRef P = Pred->getValueAsString("AssemblerCondString");
-
- if (P.empty())
+ if (!dyn_cast<DagInit>(Pred->getValue("AssemblerCondDag")->getValue()))
continue;
+ const DagInit *D = Pred->getValueAsDag("AssemblerCondDag");
+ std::string CombineType = D->getOperator()->getAsString();
+ if (CombineType != "any_of" && CombineType != "all_of")
+ PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
+ if (D->getNumArgs() == 0)
+ PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
+ bool IsOr = CombineType == "any_of";
+
if (!IsFirstEmission)
o << " && ";
- std::pair<StringRef, StringRef> pairs = P.split(',');
- while (!pairs.second.empty()) {
- emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
- o << " && ";
- pairs = pairs.second.split(',');
+ if (IsOr)
+ o << "(";
+
+ bool First = true;
+ for (auto *Arg : D->getArgs()) {
+ if (!First) {
+ if (IsOr)
+ o << " || ";
+ else
+ o << " && ";
+ }
+ if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
+ if (NotArg->getOperator()->getAsString() != "not" ||
+ NotArg->getNumArgs() != 1)
+ PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
+ Arg = NotArg->getArg(0);
+ o << "!";
+ }
+ if (!isa<DefInit>(Arg) ||
+ !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
+ PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!");
+ o << "Bits[" << Emitter->PredicateNamespace << "::" << Arg->getAsString()
+ << "]";
+
+ First = false;
}
- emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace);
+
+ if (IsOr)
+ o << ")";
+
IsFirstEmission = false;
}
return !Predicates->empty();
@@ -1229,12 +1249,8 @@
if (!Pred->getValue("AssemblerMatcherPredicate"))
continue;
- StringRef P = Pred->getValueAsString("AssemblerCondString");
-
- if (P.empty())
- continue;
-
- return true;
+ if (dyn_cast<DagInit>(Pred->getValue("AssemblerCondDag")->getValue()))
+ return true;
}
return false;
}
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 7f30b60..e64a232 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -474,19 +474,40 @@
SourceOperandMap, DestOperandMap));
}
-static void getReqFeatures(std::set<StringRef> &FeaturesSet,
- const std::vector<Record *> &ReqFeatures) {
+static void
+getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
+ std::set<std::set<std::pair<bool, StringRef>>> &AnyOfFeatureSets,
+ const std::vector<Record *> &ReqFeatures) {
for (auto &R : ReqFeatures) {
- StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
+ const DagInit *D = R->getValueAsDag("AssemblerCondDag");
+ std::string CombineType = D->getOperator()->getAsString();
+ if (CombineType != "any_of" && CombineType != "all_of")
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ if (D->getNumArgs() == 0)
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ bool IsOr = CombineType == "any_of";
+ std::set<std::pair<bool, StringRef>> AnyOfSet;
- // AsmCondString has syntax [!]F(,[!]F)*
- SmallVector<StringRef, 4> Ops;
- SplitString(AsmCondString, Ops, ",");
- assert(!Ops.empty() && "AssemblerCondString cannot be empty");
- for (auto &Op : Ops) {
- assert(!Op.empty() && "Empty operator");
- FeaturesSet.insert(Op);
+ for (auto *Arg : D->getArgs()) {
+ bool IsNot = false;
+ if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
+ if (NotArg->getOperator()->getAsString() != "not" ||
+ NotArg->getNumArgs() != 1)
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ Arg = NotArg->getArg(0);
+ IsNot = true;
+ }
+ if (!isa<DefInit>(Arg) ||
+ !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
+ PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
+ if (IsOr)
+ AnyOfSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
+ else
+ FeaturesSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
}
+
+ if (IsOr)
+ AnyOfFeatureSets.insert(AnyOfSet);
}
}
@@ -651,9 +672,10 @@
CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
}
- std::set<StringRef> FeaturesSet;
+ std::set<std::pair<bool, StringRef>> FeaturesSet;
+ std::set<std::set<std::pair<bool, StringRef>>> AnyOfFeatureSets;
// Add CompressPat required features.
- getReqFeatures(FeaturesSet, CompressPat.PatReqFeatures);
+ getReqFeatures(FeaturesSet, AnyOfFeatureSets, CompressPat.PatReqFeatures);
// Add Dest instruction required features.
std::vector<Record *> ReqFeatures;
@@ -661,19 +683,28 @@
copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
return R->getValueAsBit("AssemblerMatcherPredicate");
});
- getReqFeatures(FeaturesSet, ReqFeatures);
+ getReqFeatures(FeaturesSet, AnyOfFeatureSets, ReqFeatures);
// Emit checks for all required features.
for (auto &Op : FeaturesSet) {
- if (Op[0] == '!')
- CondStream.indent(6) << ("!STI.getFeatureBits()[" + Namespace +
- "::" + Op.substr(1) + "]")
- .str() +
- " &&\n";
- else
- CondStream.indent(6)
- << ("STI.getFeatureBits()[" + Namespace + "::" + Op + "]").str() +
- " &&\n";
+ StringRef Not = Op.first ? "!" : "";
+ CondStream.indent(6)
+ << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second + "]").str() +
+ " &&\n";
+ }
+
+ // Emit checks for all required feature groups.
+ for (auto &Set : AnyOfFeatureSets) {
+ CondStream.indent(6) << "(";
+ for (auto &Op : Set) {
+ bool isLast = &Op == &*Set.rbegin();
+ StringRef Not = Op.first ? "!" : "";
+ CondStream << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second +
+ "]").str();
+ if (!isLast)
+ CondStream << " || ";
+ }
+ CondStream << ") &&\n";
}
// Start Source Inst operands validation.
diff --git a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp b/llvm/utils/TableGen/SubtargetFeatureInfo.cpp
index e18ae47..3821f47 100644
--- a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp
+++ b/llvm/utils/TableGen/SubtargetFeatureInfo.cpp
@@ -119,33 +119,43 @@
const SubtargetFeatureInfo &SFI = SF.second;
OS << " if (";
- std::string CondStorage =
- std::string(SFI.TheDef->getValueAsString("AssemblerCondString"));
- StringRef Conds = CondStorage;
- std::pair<StringRef, StringRef> Comma = Conds.split(',');
- bool First = true;
- do {
- if (!First)
- OS << " && ";
- bool Neg = false;
- StringRef Cond = Comma.first;
- if (Cond[0] == '!') {
- Neg = true;
- Cond = Cond.substr(1);
- }
+ const DagInit *D = SFI.TheDef->getValueAsDag("AssemblerCondDag");
+ std::string CombineType = D->getOperator()->getAsString();
+ if (CombineType != "any_of" && CombineType != "all_of")
+ PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
+ if (D->getNumArgs() == 0)
+ PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
+ bool IsOr = CombineType == "any_of";
+ if (IsOr)
OS << "(";
- if (Neg)
- OS << "!";
- OS << "FB[" << TargetName << "::" << Cond << "])";
- if (Comma.second.empty())
- break;
+ bool First = true;
+ for (auto *Arg : D->getArgs()) {
+ if (!First) {
+ if (IsOr)
+ OS << " || ";
+ else
+ OS << " && ";
+ }
+ if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
+ if (NotArg->getOperator()->getAsString() != "not" ||
+ NotArg->getNumArgs() != 1)
+ PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
+ Arg = NotArg->getArg(0);
+ OS << "!";
+ }
+ if (!isa<DefInit>(Arg) ||
+ !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
+ PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!");
+ OS << "FB[" << TargetName << "::" << Arg->getAsString() << "]";
First = false;
- Comma = Comma.second.split(',');
- } while (true);
+ }
+
+ if (IsOr)
+ OS << ")";
OS << ")\n";
OS << " Features.set(" << SFI.getEnumBitName() << ");\n";