commit a2b4d3fab62382fff2b26e5bd708b06c5eb1fd5f
author Luo, Yuanke <yuanke.luo@intel.com> Thu Apr 11 15:01:03 2019 +0000
committer Luo, Yuanke <yuanke.luo@intel.com> Thu Apr 11 15:01:03 2019 +0000
tree 9337a5afc6fdaeb6205a501692cf081f6ad9772b
parent 40733618bd27dff66ef5cf0581dbb826a86e857a

[X86] Add MM register mapping from CodeView to MC register id

Differential Revision: https://reviews.llvm.org/D60437

Change-Id: I2183a6d825d0284b22705d423b88882992b236c5
llvm-svn: 358179

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
index 4a1f481..abd0d4b 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -116,6 +116,15 @@
       {codeview::RegisterId::ST6, X86::FP6},
       {codeview::RegisterId::ST7, X86::FP7},
 
+      {codeview::RegisterId::MM0, X86::MM0},
+      {codeview::RegisterId::MM1, X86::MM1},
+      {codeview::RegisterId::MM2, X86::MM2},
+      {codeview::RegisterId::MM3, X86::MM3},
+      {codeview::RegisterId::MM4, X86::MM4},
+      {codeview::RegisterId::MM5, X86::MM5},
+      {codeview::RegisterId::MM6, X86::MM6},
+      {codeview::RegisterId::MM7, X86::MM7},
+
       {codeview::RegisterId::XMM0, X86::XMM0},
       {codeview::RegisterId::XMM1, X86::XMM1},
       {codeview::RegisterId::XMM2, X86::XMM2},