[AMDGPU] Assembler: rename amd_kernel_code_t asm names according to spec
Summary:
Also removed duplicate code from AMDGPUTargetAsmStreamer.
This change only change how amd_kernel_code_t is parsed and printed. No variable names are changed.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, wdng, nhaehnle
Differential Revision: https://reviews.llvm.org/D24296
llvm-svn: 281028
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
index 36aa677..98a3f17 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_default_ci:
-; GCN: compute_pgm_rsrc1_float_mode = 192
-; GCN: compute_pgm_rsrc1_dx10_clamp = 1
-; GCN: compute_pgm_rsrc1_ieee_mode = 0
+; GCN: float_mode = 192
+; GCN: enable_dx10_clamp = 1
+; GCN: enable_ieee_mode = 0
define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -11,9 +11,9 @@
}
; GCN-LABEL: {{^}}test_default_vi:
-; GCN: compute_pgm_rsrc1_float_mode = 192
-; GCN: compute_pgm_rsrc1_dx10_clamp = 1
-; GCN: compute_pgm_rsrc1_ieee_mode = 0
+; GCN: float_mode = 192
+; GCN: enable_dx10_clamp = 1
+; GCN: enable_ieee_mode = 0
define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -21,9 +21,9 @@
}
; GCN-LABEL: {{^}}test_f64_denormals:
-; GCN: compute_pgm_rsrc1_float_mode = 192
-; GCN: compute_pgm_rsrc1_dx10_clamp = 1
-; GCN: compute_pgm_rsrc1_ieee_mode = 0
+; GCN: float_mode = 192
+; GCN: enable_dx10_clamp = 1
+; GCN: enable_ieee_mode = 0
define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -31,9 +31,9 @@
}
; GCN-LABEL: {{^}}test_f32_denormals:
-; GCN: compute_pgm_rsrc1_float_mode = 48
-; GCN: compute_pgm_rsrc1_dx10_clamp = 1
-; GCN: compute_pgm_rsrc1_ieee_mode = 0
+; GCN: float_mode = 48
+; GCN: enable_dx10_clamp = 1
+; GCN: enable_ieee_mode = 0
define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -41,9 +41,9 @@
}
; GCN-LABEL: {{^}}test_f32_f64_denormals:
-; GCN: compute_pgm_rsrc1_float_mode = 240
-; GCN: compute_pgm_rsrc1_dx10_clamp = 1
-; GCN: compute_pgm_rsrc1_ieee_mode = 0
+; GCN: float_mode = 240
+; GCN: enable_dx10_clamp = 1
+; GCN: enable_ieee_mode = 0
define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
@@ -51,9 +51,9 @@
}
; GCN-LABEL: {{^}}test_no_denormals:
-; GCN: compute_pgm_rsrc1_float_mode = 0
-; GCN: compute_pgm_rsrc1_dx10_clamp = 1
-; GCN: compute_pgm_rsrc1_ieee_mode = 0
+; GCN: float_mode = 0
+; GCN: enable_dx10_clamp = 1
+; GCN: enable_ieee_mode = 0
define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
index 099f063..4f6dbf9 100644
--- a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
@@ -18,13 +18,13 @@
; GCNHSA: .amd_kernel_code_t
-; GCNHSA: compute_pgm_rsrc2_scratch_en = 1
-; GCNHSA: compute_pgm_rsrc2_user_sgpr = 8
-; GCNHSA: compute_pgm_rsrc2_tgid_x_en = 1
-; GCNHSA: compute_pgm_rsrc2_tgid_y_en = 0
-; GCNHSA: compute_pgm_rsrc2_tgid_z_en = 0
-; GCNHSA: compute_pgm_rsrc2_tg_size_en = 0
-; GCNHSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
+; GCNHSA: enable_sgpr_private_segment_wave_byte_offset = 1
+; GCNHSA: user_sgpr_count = 8
+; GCNHSA: enable_sgpr_workgroup_id_x = 1
+; GCNHSA: enable_sgpr_workgroup_id_y = 0
+; GCNHSA: enable_sgpr_workgroup_id_z = 0
+; GCNHSA: enable_sgpr_workgroup_info = 0
+; GCNHSA: enable_vgpr_workitem_id = 0
; GCNHSA: enable_sgpr_private_segment_buffer = 1
; GCNHSA: enable_sgpr_dispatch_ptr = 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
index c22eac7..75a9ec9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
@@ -10,12 +10,12 @@
; ALL-LABEL {{^}}test_workgroup_id_x:
; HSA: .amd_kernel_code_t
-; HSA: compute_pgm_rsrc2_user_sgpr = 6
-; HSA: compute_pgm_rsrc2_tgid_x_en = 1
-; HSA: compute_pgm_rsrc2_tgid_y_en = 0
-; HSA: compute_pgm_rsrc2_tgid_z_en = 0
-; HSA: compute_pgm_rsrc2_tg_size_en = 0
-; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
+; HSA: user_sgpr_count = 6
+; HSA: enable_sgpr_workgroup_id_x = 1
+; HSA: enable_sgpr_workgroup_id_y = 0
+; HSA: enable_sgpr_workgroup_id_z = 0
+; HSA: enable_sgpr_workgroup_info = 0
+; HSA: enable_vgpr_workitem_id = 0
; HSA: enable_sgpr_grid_workgroup_count_x = 0
; HSA: enable_sgpr_grid_workgroup_count_y = 0
; HSA: enable_sgpr_grid_workgroup_count_z = 0
@@ -40,11 +40,11 @@
}
; ALL-LABEL {{^}}test_workgroup_id_y:
-; HSA: compute_pgm_rsrc2_user_sgpr = 6
-; HSA: compute_pgm_rsrc2_tgid_x_en = 1
-; HSA: compute_pgm_rsrc2_tgid_y_en = 1
-; HSA: compute_pgm_rsrc2_tgid_z_en = 0
-; HSA: compute_pgm_rsrc2_tg_size_en = 0
+; HSA: user_sgpr_count = 6
+; HSA: enable_sgpr_workgroup_id_x = 1
+; HSA: enable_sgpr_workgroup_id_y = 1
+; HSA: enable_sgpr_workgroup_id_z = 0
+; HSA: enable_sgpr_workgroup_info = 0
; HSA: enable_sgpr_grid_workgroup_count_x = 0
; HSA: enable_sgpr_grid_workgroup_count_y = 0
; HSA: enable_sgpr_grid_workgroup_count_z = 0
@@ -68,12 +68,12 @@
}
; ALL-LABEL {{^}}test_workgroup_id_z:
-; HSA: compute_pgm_rsrc2_user_sgpr = 6
-; HSA: compute_pgm_rsrc2_tgid_x_en = 1
-; HSA: compute_pgm_rsrc2_tgid_y_en = 0
-; HSA: compute_pgm_rsrc2_tgid_z_en = 1
-; HSA: compute_pgm_rsrc2_tg_size_en = 0
-; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
+; HSA: user_sgpr_count = 6
+; HSA: enable_sgpr_workgroup_id_x = 1
+; HSA: enable_sgpr_workgroup_id_y = 0
+; HSA: enable_sgpr_workgroup_id_z = 1
+; HSA: enable_sgpr_workgroup_info = 0
+; HSA: enable_vgpr_workitem_id = 0
; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_queue_ptr = 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
index 28ef7b8..393a593 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
@@ -12,7 +12,7 @@
; MESA-NEXT: .long 132{{$}}
; ALL-LABEL {{^}}test_workitem_id_x:
-; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
+; HSA: enable_vgpr_workitem_id = 0
; ALL-NOT: v0
; ALL: {{buffer|flat}}_store_dword {{.*}}v0
@@ -27,7 +27,7 @@
; MESA-NEXT: .long 2180{{$}}
; ALL-LABEL {{^}}test_workitem_id_y:
-; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1
+; HSA: enable_vgpr_workitem_id = 1
; ALL-NOT: v1
; ALL: {{buffer|flat}}_store_dword {{.*}}v1
@@ -42,7 +42,7 @@
; MESA-NEXT: .long 4228{{$}}
; ALL-LABEL {{^}}test_workitem_id_z:
-; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2
+; HSA: enable_vgpr_workitem_id = 2
; ALL-NOT: v2
; ALL: {{buffer|flat}}_store_dword {{.*}}v2
diff --git a/llvm/test/MC/AMDGPU/hsa-exp.s b/llvm/test/MC/AMDGPU/hsa-exp.s
index 0a8d0d29..488afc5 100644
--- a/llvm/test/MC/AMDGPU/hsa-exp.s
+++ b/llvm/test/MC/AMDGPU/hsa-exp.s
@@ -45,12 +45,12 @@
amd_kernel_code_t_minimal:
.amd_kernel_code_t
- kernel_code_version_major = .option.machine_version_major
+ amd_code_version_major = .option.machine_version_major
enable_sgpr_kernarg_segment_ptr = 1
is_ptr64 = my_is_ptr64
- compute_pgm_rsrc1_vgprs = 1
- compute_pgm_rsrc1_sgprs = 1+(my_sgpr-1)/8
- compute_pgm_rsrc2_user_sgpr = 2
+ granulated_workitem_vgpr_count = 1
+ granulated_wavefront_sgpr_count = 1+(my_sgpr-1)/8
+ user_sgpr_count = 2
kernarg_segment_byte_size = my_kernarg_segment_byte_size
wavefront_sgpr_count = my_sgpr
// wavefront_sgpr_count = 7
@@ -58,39 +58,39 @@
// Make sure a blank line won't break anything:
// Make sure a line with whitespace won't break anything:
-
+
workitem_vgpr_count = 16
.end_amd_kernel_code_t
// ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
// ASM: .amd_kernel_code_t
-// ASM: kernel_code_version_major = 7
-// ASM: kernel_code_version_minor = 0
-// ASM: machine_kind = 1
-// ASM: machine_version_major = 7
-// ASM: machine_version_minor = 0
-// ASM: machine_version_stepping = 0
+// ASM: amd_code_version_major = 7
+// ASM: amd_code_version_minor = 0
+// ASM: amd_machine_kind = 1
+// ASM: amd_machine_version_major = 7
+// ASM: amd_machine_version_minor = 0
+// ASM: amd_machine_version_stepping = 0
// ASM: kernel_code_entry_byte_offset = 256
// ASM: kernel_code_prefetch_byte_size = 0
// ASM: max_scratch_backing_memory_byte_size = 0
-// ASM: compute_pgm_rsrc1_vgprs = 1
-// ASM: compute_pgm_rsrc1_sgprs = 1
-// ASM: compute_pgm_rsrc1_priority = 0
-// ASM: compute_pgm_rsrc1_float_mode = 0
-// ASM: compute_pgm_rsrc1_priv = 0
-// ASM: compute_pgm_rsrc1_dx10_clamp = 0
-// ASM: compute_pgm_rsrc1_debug_mode = 0
-// ASM: compute_pgm_rsrc1_ieee_mode = 0
-// ASM: compute_pgm_rsrc2_scratch_en = 0
-// ASM: compute_pgm_rsrc2_user_sgpr = 2
-// ASM: compute_pgm_rsrc2_tgid_x_en = 0
-// ASM: compute_pgm_rsrc2_tgid_y_en = 0
-// ASM: compute_pgm_rsrc2_tgid_z_en = 0
-// ASM: compute_pgm_rsrc2_tg_size_en = 0
-// ASM: compute_pgm_rsrc2_tidig_comp_cnt = 0
-// ASM: compute_pgm_rsrc2_excp_en_msb = 0
-// ASM: compute_pgm_rsrc2_lds_size = 0
-// ASM: compute_pgm_rsrc2_excp_en = 0
+// ASM: granulated_workitem_vgpr_count = 1
+// ASM: granulated_wavefront_sgpr_count = 1
+// ASM: priority = 0
+// ASM: float_mode = 0
+// ASM: priv = 0
+// ASM: enable_dx10_clamp = 0
+// ASM: debug_mode = 0
+// ASM: enable_ieee_mode = 0
+// ASM: enable_sgpr_private_segment_wave_byte_offset = 0
+// ASM: user_sgpr_count = 2
+// ASM: enable_sgpr_workgroup_id_x = 0
+// ASM: enable_sgpr_workgroup_id_y = 0
+// ASM: enable_sgpr_workgroup_id_z = 0
+// ASM: enable_sgpr_workgroup_info = 0
+// ASM: enable_vgpr_workitem_id = 0
+// ASM: enable_exception_msb = 0
+// ASM: granulated_lds_size = 0
+// ASM: enable_exception = 0
// ASM: enable_sgpr_private_segment_buffer = 0
// ASM: enable_sgpr_dispatch_ptr = 0
// ASM: enable_sgpr_queue_ptr = 0
diff --git a/llvm/test/MC/AMDGPU/hsa.s b/llvm/test/MC/AMDGPU/hsa.s
index 27de3d5..b95a790 100644
--- a/llvm/test/MC/AMDGPU/hsa.s
+++ b/llvm/test/MC/AMDGPU/hsa.s
@@ -42,99 +42,99 @@
amd_kernel_code_t_test_all:
; Test all amd_kernel_code_t members with non-default values.
.amd_kernel_code_t
- kernel_code_version_major = 100
- kernel_code_version_minor = 100
- machine_kind = 0
- machine_version_major = 5
- machine_version_minor = 5
- machine_version_stepping = 5
- kernel_code_entry_byte_offset = 512
- kernel_code_prefetch_byte_size = 1
- max_scratch_backing_memory_byte_size = 1
- compute_pgm_rsrc1_vgprs = 1
- compute_pgm_rsrc1_sgprs = 1
- compute_pgm_rsrc1_priority = 1
- compute_pgm_rsrc1_float_mode = 1
- compute_pgm_rsrc1_priv = 1
- compute_pgm_rsrc1_dx10_clamp = 1
- compute_pgm_rsrc1_debug_mode = 1
- compute_pgm_rsrc1_ieee_mode = 1
- compute_pgm_rsrc2_scratch_en = 1
- compute_pgm_rsrc2_user_sgpr = 1
- compute_pgm_rsrc2_tgid_x_en = 1
- compute_pgm_rsrc2_tgid_y_en = 1
- compute_pgm_rsrc2_tgid_z_en = 1
- compute_pgm_rsrc2_tg_size_en = 1
- compute_pgm_rsrc2_tidig_comp_cnt = 1
- compute_pgm_rsrc2_excp_en_msb = 1
- compute_pgm_rsrc2_lds_size = 1
- compute_pgm_rsrc2_excp_en = 1
- enable_sgpr_private_segment_buffer = 1
- enable_sgpr_dispatch_ptr = 1
- enable_sgpr_queue_ptr = 1
- enable_sgpr_kernarg_segment_ptr = 1
- enable_sgpr_dispatch_id = 1
- enable_sgpr_flat_scratch_init = 1
- enable_sgpr_private_segment_size = 1
- enable_sgpr_grid_workgroup_count_x = 1
- enable_sgpr_grid_workgroup_count_y = 1
- enable_sgpr_grid_workgroup_count_z = 1
- enable_ordered_append_gds = 1
- private_element_size = 1
- is_ptr64 = 1
- is_dynamic_callstack = 1
- is_debug_enabled = 1
- is_xnack_enabled = 1
- workitem_private_segment_byte_size = 1
- workgroup_group_segment_byte_size = 1
- gds_segment_byte_size = 1
- kernarg_segment_byte_size = 1
- workgroup_fbarrier_count = 1
- wavefront_sgpr_count = 1
- workitem_vgpr_count = 1
- reserved_vgpr_first = 1
- reserved_vgpr_count = 1
- reserved_sgpr_first = 1
- reserved_sgpr_count = 1
- debug_wavefront_private_segment_offset_sgpr = 1
- debug_private_segment_buffer_sgpr = 1
- kernarg_segment_alignment = 5
- group_segment_alignment = 5
- private_segment_alignment = 5
- wavefront_size = 5
- call_convention = 1
- runtime_loader_kernel_symbol = 1
+ kernel_code_version_major = 100
+ kernel_code_version_minor = 100
+ machine_kind = 0
+ machine_version_major = 5
+ machine_version_minor = 5
+ machine_version_stepping = 5
+ kernel_code_entry_byte_offset = 512
+ kernel_code_prefetch_byte_size = 1
+ max_scratch_backing_memory_byte_size = 1
+ compute_pgm_rsrc1_vgprs = 1
+ compute_pgm_rsrc1_sgprs = 1
+ compute_pgm_rsrc1_priority = 1
+ compute_pgm_rsrc1_float_mode = 1
+ compute_pgm_rsrc1_priv = 1
+ compute_pgm_rsrc1_dx10_clamp = 1
+ compute_pgm_rsrc1_debug_mode = 1
+ compute_pgm_rsrc1_ieee_mode = 1
+ compute_pgm_rsrc2_scratch_en = 1
+ compute_pgm_rsrc2_user_sgpr = 1
+ compute_pgm_rsrc2_tgid_x_en = 1
+ compute_pgm_rsrc2_tgid_y_en = 1
+ compute_pgm_rsrc2_tgid_z_en = 1
+ compute_pgm_rsrc2_tg_size_en = 1
+ compute_pgm_rsrc2_tidig_comp_cnt = 1
+ compute_pgm_rsrc2_excp_en_msb = 1
+ compute_pgm_rsrc2_lds_size = 1
+ compute_pgm_rsrc2_excp_en = 1
+ enable_sgpr_private_segment_buffer = 1
+ enable_sgpr_dispatch_ptr = 1
+ enable_sgpr_queue_ptr = 1
+ enable_sgpr_kernarg_segment_ptr = 1
+ enable_sgpr_dispatch_id = 1
+ enable_sgpr_flat_scratch_init = 1
+ enable_sgpr_private_segment_size = 1
+ enable_sgpr_grid_workgroup_count_x = 1
+ enable_sgpr_grid_workgroup_count_y = 1
+ enable_sgpr_grid_workgroup_count_z = 1
+ enable_ordered_append_gds = 1
+ private_element_size = 1
+ is_ptr64 = 1
+ is_dynamic_callstack = 1
+ is_debug_enabled = 1
+ is_xnack_enabled = 1
+ workitem_private_segment_byte_size = 1
+ workgroup_group_segment_byte_size = 1
+ gds_segment_byte_size = 1
+ kernarg_segment_byte_size = 1
+ workgroup_fbarrier_count = 1
+ wavefront_sgpr_count = 1
+ workitem_vgpr_count = 1
+ reserved_vgpr_first = 1
+ reserved_vgpr_count = 1
+ reserved_sgpr_first = 1
+ reserved_sgpr_count = 1
+ debug_wavefront_private_segment_offset_sgpr = 1
+ debug_private_segment_buffer_sgpr = 1
+ kernarg_segment_alignment = 5
+ group_segment_alignment = 5
+ private_segment_alignment = 5
+ wavefront_size = 5
+ call_convention = 1
+ runtime_loader_kernel_symbol = 1
.end_amd_kernel_code_t
// ASM-LABEL: {{^}}amd_kernel_code_t_test_all:
// ASM: .amd_kernel_code_t
-// ASM: kernel_code_version_major = 100
-// ASM: kernel_code_version_minor = 100
-// ASM: machine_kind = 0
-// ASM: machine_version_major = 5
-// ASM: machine_version_minor = 5
-// ASM: machine_version_stepping = 5
+// ASM: amd_code_version_major = 100
+// ASM: amd_code_version_minor = 100
+// ASM: amd_machine_kind = 0
+// ASM: amd_machine_version_major = 5
+// ASM: amd_machine_version_minor = 5
+// ASM: amd_machine_version_stepping = 5
// ASM: kernel_code_entry_byte_offset = 512
// ASM: kernel_code_prefetch_byte_size = 1
// ASM: max_scratch_backing_memory_byte_size = 1
-// ASM: compute_pgm_rsrc1_vgprs = 1
-// ASM: compute_pgm_rsrc1_sgprs = 1
-// ASM: compute_pgm_rsrc1_priority = 1
-// ASM: compute_pgm_rsrc1_float_mode = 1
-// ASM: compute_pgm_rsrc1_priv = 1
-// ASM: compute_pgm_rsrc1_dx10_clamp = 1
-// ASM: compute_pgm_rsrc1_debug_mode = 1
-// ASM: compute_pgm_rsrc1_ieee_mode = 1
-// ASM: compute_pgm_rsrc2_scratch_en = 1
-// ASM: compute_pgm_rsrc2_user_sgpr = 1
-// ASM: compute_pgm_rsrc2_tgid_x_en = 1
-// ASM: compute_pgm_rsrc2_tgid_y_en = 1
-// ASM: compute_pgm_rsrc2_tgid_z_en = 1
-// ASM: compute_pgm_rsrc2_tg_size_en = 1
-// ASM: compute_pgm_rsrc2_tidig_comp_cnt = 1
-// ASM: compute_pgm_rsrc2_excp_en_msb = 1
-// ASM: compute_pgm_rsrc2_lds_size = 1
-// ASM: compute_pgm_rsrc2_excp_en = 1
+// ASM: granulated_workitem_vgpr_count = 1
+// ASM: granulated_wavefront_sgpr_count = 1
+// ASM: priority = 1
+// ASM: float_mode = 1
+// ASM: priv = 1
+// ASM: enable_dx10_clamp = 1
+// ASM: debug_mode = 1
+// ASM: enable_ieee_mode = 1
+// ASM: enable_sgpr_private_segment_wave_byte_offset = 1
+// ASM: user_sgpr_count = 1
+// ASM: enable_sgpr_workgroup_id_x = 1
+// ASM: enable_sgpr_workgroup_id_y = 1
+// ASM: enable_sgpr_workgroup_id_z = 1
+// ASM: enable_sgpr_workgroup_info = 1
+// ASM: enable_vgpr_workitem_id = 1
+// ASM: enable_exception_msb = 1
+// ASM: granulated_lds_size = 1
+// ASM: enable_exception = 1
// ASM: enable_sgpr_private_segment_buffer = 1
// ASM: enable_sgpr_dispatch_ptr = 1
// ASM: enable_sgpr_queue_ptr = 1
@@ -176,9 +176,9 @@
.amd_kernel_code_t
enable_sgpr_kernarg_segment_ptr = 1
is_ptr64 = 1
- compute_pgm_rsrc1_vgprs = 1
- compute_pgm_rsrc1_sgprs = 1
- compute_pgm_rsrc2_user_sgpr = 2
+ granulated_workitem_vgpr_count = 1
+ granulated_wavefront_sgpr_count = 1
+ user_sgpr_count = 2
kernarg_segment_byte_size = 16
wavefront_sgpr_count = 8
// wavefront_sgpr_count = 7
@@ -186,39 +186,39 @@
// Make sure a blank line won't break anything:
// Make sure a line with whitespace won't break anything:
-
+
workitem_vgpr_count = 16
.end_amd_kernel_code_t
// ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
// ASM: .amd_kernel_code_t
-// ASM: kernel_code_version_major = 1
-// ASM: kernel_code_version_minor = 0
-// ASM: machine_kind = 1
-// ASM: machine_version_major = 7
-// ASM: machine_version_minor = 0
-// ASM: machine_version_stepping = 0
+// ASM: amd_code_version_major = 1
+// ASM: amd_code_version_minor = 0
+// ASM: amd_machine_kind = 1
+// ASM: amd_machine_version_major = 7
+// ASM: amd_machine_version_minor = 0
+// ASM: amd_machine_version_stepping = 0
// ASM: kernel_code_entry_byte_offset = 256
// ASM: kernel_code_prefetch_byte_size = 0
// ASM: max_scratch_backing_memory_byte_size = 0
-// ASM: compute_pgm_rsrc1_vgprs = 1
-// ASM: compute_pgm_rsrc1_sgprs = 1
-// ASM: compute_pgm_rsrc1_priority = 0
-// ASM: compute_pgm_rsrc1_float_mode = 0
-// ASM: compute_pgm_rsrc1_priv = 0
-// ASM: compute_pgm_rsrc1_dx10_clamp = 0
-// ASM: compute_pgm_rsrc1_debug_mode = 0
-// ASM: compute_pgm_rsrc1_ieee_mode = 0
-// ASM: compute_pgm_rsrc2_scratch_en = 0
-// ASM: compute_pgm_rsrc2_user_sgpr = 2
-// ASM: compute_pgm_rsrc2_tgid_x_en = 0
-// ASM: compute_pgm_rsrc2_tgid_y_en = 0
-// ASM: compute_pgm_rsrc2_tgid_z_en = 0
-// ASM: compute_pgm_rsrc2_tg_size_en = 0
-// ASM: compute_pgm_rsrc2_tidig_comp_cnt = 0
-// ASM: compute_pgm_rsrc2_excp_en_msb = 0
-// ASM: compute_pgm_rsrc2_lds_size = 0
-// ASM: compute_pgm_rsrc2_excp_en = 0
+// ASM: granulated_workitem_vgpr_count = 1
+// ASM: granulated_wavefront_sgpr_count = 1
+// ASM: priority = 0
+// ASM: float_mode = 0
+// ASM: priv = 0
+// ASM: enable_dx10_clamp = 0
+// ASM: debug_mode = 0
+// ASM: enable_ieee_mode = 0
+// ASM: enable_sgpr_private_segment_wave_byte_offset = 0
+// ASM: user_sgpr_count = 2
+// ASM: enable_sgpr_workgroup_id_x = 0
+// ASM: enable_sgpr_workgroup_id_y = 0
+// ASM: enable_sgpr_workgroup_id_z = 0
+// ASM: enable_sgpr_workgroup_info = 0
+// ASM: enable_vgpr_workitem_id = 0
+// ASM: enable_exception_msb = 0
+// ASM: granulated_lds_size = 0
+// ASM: enable_exception = 0
// ASM: enable_sgpr_private_segment_buffer = 0
// ASM: enable_sgpr_dispatch_ptr = 0
// ASM: enable_sgpr_queue_ptr = 0